10 ps jitter 2 clock cycle lock time CMOS digital clock generator based on an interleaved synchronous mirror delay scheme

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1997, Pages 109-110

  Saeki, Takanori ^a   Nakamura, Hideyuki ^a   Shimizu, Junzoh ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DELAY CIRCUITS;

DIGITAL CLOCK GENERATORS; JITTER; SYNCHRONOUS MIRROR DELAY (SMD) SCHEME;

TIMING CIRCUITS;

EID: 0031346280     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)