A closed-form back-gate-bias related inverse narrow-channel effect model for deep-submicron VLSI CMOS devices using shallow trench isolation

IEEE Transactions on Electron Devices

Volumn 47, Issue 4, 2000, Pages 725-733

  Lin, Shih Chia ^a   Kuo, James B ^b   Huang, Kuo Tai ^b   Sun, Shih Wei ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

Conformai mapping technique; Inverse narrow channel effect; Small geometry; STI

Indexed keywords

COMPUTATIONAL GEOMETRY; COMPUTER SIMULATION; CONFORMAL MAPPING; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS; THRESHOLD VOLTAGE; VLSI CIRCUITS;

DEEP SUBMICRON DEVICES; INVERSE NARROW CHANNEL EFFECT; SHALLOW TRENCH ISOLATION (STI);

CMOS INTEGRATED CIRCUITS;

EID: 0033884611     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.830986     Document Type: Article

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