An Analytical Drain Current Model Considering Both Electron and Lattice Temperatures Simultaneously for Deep Submicron Ultrathin SOI NMOS Devices with Self-Heating

IEEE Transactions on Electron Devices

Volumn 42, Issue 5, 1995, Pages 899-906

  Chen, Yu Guang ^a   Ma, Shyh Yih ^a   Kuo, James B ^a   Yu, Zhiping ^b   Dutton, Robert W ^b  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; HEAT CONDUCTION; HEATING; MOS DEVICES; NEGATIVE RESISTANCE; SILICON ON INSULATOR TECHNOLOGY; TEMPERATURE;

CLOSED FORM ANALYTICAL DRAIN CURRENT MODEL; DEEP SUBMICRON ULTRATHIN DEVICES; DRAIN CURRENT MODEL; ELECTRON TEMPERATURE; LATTICE TEMPERATURE; TWO DIMENSIONAL DEVICE;

SEMICONDUCTOR DEVICE MODELS;

EID: 0029307806     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.381986     Document Type: Article

References (22)

1. M. Yoshimi, M. Takahashi, S. Kambayashi, M. Kemmochi, H. Hazama, T. Wada, K. Kato, H. Tango, and K. Natori, “Electrical properties and technological perspectives of thin-film SOI MOSFETs,” IEICE Trans., vol. 74, no. 2 pp. 337–351, Feb. 1991.
2. D. K. Sharma, J. Gautier, and G. Merckel, “Negative dynamic resistance in MOS devices,” IEEE J. Solid-State Circuits, vol. 13, no. 3, pp. 378–380, 1978.
3. L. T. Su, J. E. Chung, D. A. Antoniadis, K. E. Goodson, and M. I. Flik, “Measurement and modeling of self-heating in SOI NMOSFET's,” IEEE Trans. Electron Devices, vol. 41, no. 1, pp. 69–75, Jan. 1994.
4. L. T. Su, K. E. Goodson, D. A. Antoniadis, M. I. Flik, and J. E. Chung, “Measurement and modeling of self-heating effects in SOI NMOSFETs,” IEDM Tech. Dig., 1992, pp. 357–360.
5. Z. Chai and M. Berger, “The self-heating effect and its influence on the electrical properties of SOI MOSFET's,” in Proc. IEEE SOI/SOS Tech. Conf., 1992, pp. 78–79.
6. R. J. T. Bunyan, M. J. Uren, J. C. Alderman, and W. Eccleston, “Use of noise thermometry to study the effects of self-heating in submicrometer SOI MOSFET's,” IEEE Electron Device Lett., vol. 13, no. 5, pp. 279–281, May 1992.
7. N. Yasuda, S. Ueno, K. Taniguchi, C. Hamaguchi, Y. Yamaguchi, and T. Nishimura, “Analytical device model of SOI MOSFET's including self-heating effect,” Japan J. Applied Physics, vol. 30, no. 12B, pp. 3677–3684, Dec. 1991.
8. L. J. McDaid, S. Hall, P. H. Mellor, W. Eccleston, and J. C. Alderman, “Physical origin of negative differential resistance in SOI transistors,” Electron. Lett., vol. 25, no. 13, pp. 827–828, June 1989.
9. N. Kistler, E. V. Ploeg, J. Woo, and J. D. Plummer, “Sub-quarter-micrometer CMOS on ultrathin (400 Å) SOI,” IEEE Electron Device Lett., vol. 13, no. 5, pp. 235–237, May 1992.
10. D. Hisamoto, K. Nakamura, M. Saito, N. Kobayashi, S. Kimura, R. Nagai, T. Nishida, and E. Takeda, “Ultrathin SOI CMOS with selective CVD tungsten for low resistance source and drain,” IEDM Tech. Dig., 1992, pp. 829–832.
11. Y. Omura, S. Nakashima, K. lzumi, and T. Ishii, “0.1 µm-gate ultrathin-film CMOS devices using SIMOX substrate with 80-nm-thick buried oxide layer.” IEDM Tech. Dig. 1991, pp. 675–678, 1991.
12. K. Sonoda, K. Taniguchi, and C. Hamaguchi, “Analytical device model for submicrometer MOSFET's,” IEEE Trans. Electron Devices, vol. 38, no. 12, pp. 2662–2668, Dec. 1991.
13. S. Y. Ma and J. B. Kuo, “Concise analytical model for deep submicron NMOS devices with consideration of energy transport,” Japan J. Appl. Phys., vol. 33, pp. 550–553, Jan. 1994.
14. C. M. Liu, J. B. Kuo, and Y. P. Wu, “An analytical quasi-saturation model considering heat flow for a DMOS device,” IEEE Trans. Electron Devices. vol. 41. no. 6. pp. 952–958. June 1994.
15. H.-K. Lim and J. G. Fossum, “Current-voltage characteristics of thin-film SOI MOSFET's in strong inversion,” IEEE Trans. Electron Devices, vol. 31, no. 4, pp. 401–408, 1984.
16. Y. A. El-Mansy and A. R. Boothroyd, “A simple two-dimensional model for IGFET operation in the saturation region, “ IEEE Trans. Electron Devices, vol. 24, no. 3, pp. 254–262, Mar. 1987.
17. H. C. Chow, W. S. Feng, and J. B. Kuo, “An improved analytical short-channel MOSFET model valid in all regions of operation for analog/digital circuit simulation,” IEEE Trans. CAD of IC, vol. 11 no. 1 2, pp. 1522–1528, Dec. 1992.
18. K. Mayaram, J. C. Lee, and C. Hu, “A model for the electric field i n lightly doped drain structures,” IEEE Trans. Electron Devices, vol. 34, no. 7. pp. 1509–1518, July 1987.
19. N. G. Einspruch and G. Gildenblat, “Advanced MOS devices physics.” New York: Academic Press, 1989, vol. 18, pp. 28.
20. R.-H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET: From bulk to SOI to bulk, ” IEEE Trans. Electron Devices, vol. 37, no. 7, pp. 1704–1710, 1992.
21. J. Chen, S. Parke, J. King, F. Assaderaghi, P. K. Ko, and C. Hu, “A high speed SOI technology with 12 ps/18 ps gate delay operating at 5 V/1.5 V,” IEDM Tech. Dig., 1992, pp. 35–38.
22. J. Y. Choi and J. G. Fossum, “Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET's,” IEEE Trans. Electron Devices, vol. 38, pp. 1384–1391, June 1991.