A Novel 0.25 μm Shallow Trench Isolation Technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 837-840

  Chen, C ^a   Chou, J W ^a   Lur, W ^a   Sun, S W ^a  

^a UNITED MICROELECTRONICS CORPORATION   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CHEMICAL VAPOR DEPOSITION; GATES (TRANSISTOR); LOGIC CIRCUITS; MOSFET DEVICES; NITRIDES; OXIDES; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE; SUBSTRATES; VLSI CIRCUITS;

0.25 ΜM; CHANNEL IMPLANTS; ENERGY WELLS; GATE OXIDE; ISOLATION TECHNOLOGY; KINK EFFECT; MOSFETS; SHALLOW-TRENCH-ISOLATED; SUBTHRESHOLD CONDUCTION; TRENCH ISOLATION;

MOSFET DEVICES; INTEGRATED CIRCUIT MANUFACTURE;

POLYSILICON; SHALLOW TRENCH ISOLATION TECHNOLOGY;

EID: 0030398050     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iedm.1996.554110     Document Type: Conference Paper

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