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Volumn , Issue , 1999, Pages 369-374

Testing the logic cells and interconnect resources for FPGAs

Author keywords

[No Author keywords available]

Indexed keywords

CONFIGURABLE LOGIC BLOCKS (CLB); STATIC RANDOM ACCESS MEMORY (SRAM);

EID: 0033321656     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article
Times cited : (30)

References (9)
  • 2
    • 84895122640 scopus 로고    scopus 로고
    • Design of an automatic testing for FPGAs
    • to appear in
    • A. Doumar, T. Ohmameuda, and H. Ito, "Design of an Automatic Testing for FPGAs, " to appear in IEEE European Test Workshop. 1999, http://www.icsd2.tj.chiba-u.ac.Jp/~doumar/p029.ps.
    • (1999) IEEE European Test Workshop
    • Doumar, A.1    Ohmameuda, T.2    Ito, H.3
  • 4
    • 0032099764 scopus 로고    scopus 로고
    • Testing configurable LUT-Based FPGA's
    • June
    • W. K. Huang, F. J. Meyer and F. Lombardi, "Testing Configurable LUT-Based FPGA's, " IEEE trans, on VLSI, Vol. 6, No. 2, pp. 276-283, June 1998.
    • (1998) IEEE Trans, on VLSI , vol.6 , Issue.2 , pp. 276-283
    • Huang, W.K.1    Meyer, F.J.2    Lombardi, F.3
  • 6
    • 0030652669 scopus 로고    scopus 로고
    • Test of RAM-Based FPGA: Methodology and Application to the interconnect structure
    • IEEE CS Press
    • M. RenoveU, J. Figueras, and Y. Zorian, "Test of RAM-Based FPGA: Methodology and Application to the interconnect structure, " Proc. 15th IEEE VLSI Test symp., IEEE CS Press, pp. 204-209, 1997.
    • (1997) Proc. 15th IEEE VLSI Test Symp , pp. 204-209
    • Renoveu, M.1    Figueras, J.2    Zorian, Y.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.