메뉴 건너뛰기




Volumn 42, Issue 11, 1995, Pages 1940-1948

Analytical Models for n+-p+ Double-Gate SOI MOSFET's

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; GATES (TRANSISTOR); MATHEMATICAL MODELS; NUMERICAL ANALYSIS; SEMICONDUCTOR DOPING;

EID: 0029403527     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.469401     Document Type: Article
Times cited : (95)

References (35)
  • 3
    • 0019075967 scopus 로고
    • The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI
    • P. Chatterjee, W. R. Hunter, T. C. Holloway, and Y. T. Lin, “The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI,” IEEE Electron Device Lett., vol. EDL-1, pp. 220-223, 1980.
    • (1980) IEEE Electron Device Lett. , vol.1 EDL , pp. 220-223
    • Chatterjee, P.1    Hunter, W.R.2    Holloway, T.C.3    Lin, Y.T.4
  • 4
    • 0021406605 scopus 로고
    • Generalized scaling theory and its application to a 1/4 micrometer MOSFET design
    • G. Baccarani, M. R. Wordeman, and R. H. Dennard, “Generalized scaling theory and its application to a 1/4 micrometer MOSFET design,” IEEE Trans. Electron Devices, vol. ED-31, pp. 452-462, 1984.
    • (1984) IEEE Trans. Electron Devices , vol.31 ED , pp. 452-462
    • Baccarani, G.1    Wordeman, M.R.2    Dennard, R.H.3
  • 5
    • 0022135706 scopus 로고
    • Dependence of channel electric field on device scaling
    • T. Y. Chan, P. K. Ko, and C. Hu, “Dependence of channel electric field on device scaling,” IEEE Electron Device Lett., vol. EDL-6, pp. 551-553, 1985.
    • (1985) IEEE Electron Device Lett. , vol.6 EDL , pp. 551-553
    • Chan, T.Y.1    Ko, P.K.2    Hu, C.3
  • 6
    • 6344290643 scopus 로고
    • Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate
    • T. Sekigawa and Y. Hayashi, “Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate,” Solid-State Electron., vol. 27, pp. 827-828, 1984.
    • (1984) Solid-State Electron. , vol.27 , pp. 827-828
    • Sekigawa, T.1    Hayashi, Y.2
  • 8
    • 0026169335 scopus 로고
    • Impact of the vertical SOI ‘DELTA’ structure on planar device technology
    • D. Hisamoto, T. Kaga, and E. Takeda, “Impact of the vertical SOI ‘DELTA’ structure on planar device technology,” IEEE Trans. Electron Devices, vol. 38, pp. 1419-1424, 1991.
    • (1991) IEEE Trans. Electron Devices , vol.38 , pp. 1419-1424
    • Hisamoto, D.1    Kaga, T.2    Takeda, E.3
  • 9
    • 0025749775 scopus 로고
    • Fabrication of double-gate thin-film SOI MOSFET's using wafer bonding and polishing
    • H. Horie, S. Ando, T. Tanaka, M. Imai, Y. Arimoto, and S. Hijiya, “Fabrication of double-gate thin-film SOI MOSFET's using wafer bonding and polishing,” in 1991 SSDM Tech. Dig., pp. 165-167.
    • (1991) SSDM Tech. Dig. , pp. 165-167
    • Horie, H.1    Ando, S.2    Tanaka, T.3    Imai, M.4    Arimoto, Y.5    Hijiya, S.6
  • 10
    • 84954092771 scopus 로고
    • Analysis of p+ double-gate thin-film SOI MOSFET's
    • T. Tanaka, H. Horie, S. Ando, and S. Hijiya, “Analysis of p+ double-gate thin-film SOI MOSFET's,” in 1991 IEDM Tech. Dig., pp. 683-686.
    • (1991) IEDM Tech. Dig. , pp. 683-686
    • Tanaka, T.1    Horie, H.2    Ando, S.3    Hijiya, S.4
  • 11
    • 85056911965 scopus 로고
    • Monte Carlo simulation of a 30- nm dual-gate MOSFET: How short can Si go?
    • D. J. Frank, S. E. Laux, and M. V. Fischetti, “Monte Carlo simulation of a 30- nm dual-gate MOSFET: How short can Si go?,” in 1991 IEDM Tech. Dig., pp. 553-556.
    • (1991) IEDM Tech. Dig. , pp. 553-556
    • Frank, D.J.1    Laux, S.E.2    Fischetti, M.V.3
  • 12
    • 0023421993 scopus 로고
    • Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
    • F. Balestra, S. Cristoloveanu, M. Benachir, and T. Elewa, “Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,” IEEE Electron Device Lett., vol. EDL-8, pp. 410-412, 1987.
    • (1987) IEEE Electron Device Lett. , vol.8 EDL , pp. 410-412
    • Balestra, F.1    Cristoloveanu, S.2    Benachir, M.3    Elewa, T.4
  • 13
    • 0026763758 scopus 로고
    • Dual-gate operation and volume inversion in n-channel SOI MOSFET's
    • S. Venkatesan, G. W. Neudeck, and R. F. Pierret, “Dual-gate operation and volume inversion in n-channel SOI MOSFET's,” IEEE Electron Device Lett., vol. 13, pp. 44-46, 1992.
    • (1992) IEEE Electron Device Lett. , vol.13 , pp. 44-46
    • Venkatesan, S.1    Neudeck, G.W.2    Pierret, R.F.3
  • 14
    • 84907777860 scopus 로고
    • An analytical model for GAA transistors
    • A. Terao and F. van de Wiele, “An analytical model for GAA transistors,” Microelectron. Eng., vol. 15, pp. 233-236, 1991.
    • (1991) Microelectron. Eng. , vol.15 , pp. 233-236
    • Terao, A.1    van de Wiele, F.2
  • 15
    • 0026927930 scopus 로고
    • Characteristics of nMOS/GAA (Gate-All-Around) transistors near threshold voltage
    • P. Francis, A. Terao, D. Flandre, and F. van de Wiele, “Characteristics of nMOS/GAA (Gate-All-Around) transistors near threshold voltage,” Microelectron. Eng., vol. 19, pp. 815-818, 1992.
    • (1992) Microelectron. Eng. , vol.19 , pp. 815-818
    • Francis, P.1    Terao, A.2    Flandre, D.3    van de Wiele, F.4
  • 16
    • 0026103660 scopus 로고
    • Threshold slope of the volume-inversion MOS transistor
    • J. Brini, M. Benachir, G. Ghibaudo, and F. Balestra, “Threshold slope of the volume-inversion MOS transistor,” IEE Proc. G, vol. 138, pp. 133-136, 1991.
    • (1991) IEE Proc. G , vol.138 , pp. 133-136
    • Brini, J.1    Benachir, M.2    Ghibaudo, G.3    Balestra, F.4
  • 17
    • 0028378433 scopus 로고
    • Analytical surface potential expression for thin-film double-gate SOI MOSFET's
    • K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, Y. Arimoto, and T. Itoh, “Analytical surface potential expression for thin-film double-gate SOI MOSFET's,” Solid-State Electron., vol. 37, pp. 327-332, 1994.
    • (1994) Solid-State Electron. , vol.37 , pp. 327-332
    • Suzuki, K.1    Tanaka, T.2    Tosaka, Y.3    Horie, H.4    Arimoto, Y.5    Itoh, T.6
  • 18
    • 0027697702 scopus 로고
    • Analytical models for symmetric thin-film double-gate silicon-on-insulator metal-oxide-semiconductor-field-effect-transistors
    • K. Suzuki, S. Satoh, T. Tanaka, and S. Ando, “Analytical models for symmetric thin-film double-gate silicon-on-insulator metal-oxide-semiconductor-field-effect-transistors,” Jpn. J. Appl. Phys., vol. 32, pp. 4916-4922, 1993.
    • (1993) Jpn. J. Appl. Phys. , vol.32 , pp. 4916-4922
    • Suzuki, K.1    Satoh, S.2    Tanaka, T.3    Ando, S.4
  • 19
    • 0026896303 scopus 로고
    • Scaling the Si MOSFET; from bulk to SOI to bulk
    • R. H. Yan, A. Ourmazd, and K. F. Lee, “Scaling the Si MOSFET; from bulk to SOI to bulk,” IEEE Trans. Electron Devices, vol. 39, pp. 1704-1710, 1992.
    • (1992) IEEE Trans. Electron Devices , vol.39 , pp. 1704-1710
    • Yan, R.H.1    Ourmazd, A.2    Lee, K.F.3
  • 21
    • 0024130103 scopus 로고
    • Bipolar circuit simulation system using two-dimensional simulator
    • S. Satoh, H. Oka, and N. Noriaki, “Bipolar circuit simulation system using two-dimensional simulator,” Fujitsu Sci. Tech. J., vol. 24, pp. 456-463, 1988.
    • (1988) Fujitsu Sci. Tech. J. , vol.24 , pp. 456-463
    • Satoh, S.1    Oka, H.2    Noriaki, N.3
  • 22
    • 85027182855 scopus 로고    scopus 로고
    • Novel polysilicon/TiN structure for fully depleted SOUCMOS
    • J. M. Hwang and G. Pollack, “Novel polysilicon/TiN structure for fully depleted SOUCMOS,” in 7992 IEDM Tech. Dig, pp. 345-348.
    • in 7992 IEDM Tech. Dig , pp. 345-348
    • Hwang, J.M.1    Pollack, G.2
  • 23
    • 0028532218 scopus 로고
    • Ultrafast operation of Vth-adjusted p+-n+ double-gate SOI MOSFET's
    • T. Tanaka, K. Suzuki, H. Horie, and T. Sugii, “Ultrafast operation of Vth-adjusted p+-n+ double-gate SOI MOSFET's,” IEEE Electron Device Lett., vol. 15, pp. 386-388, 1994.
    • (1994) IEEE Electron Device Lett. , vol.15 , pp. 386-388
    • Tanaka, T.1    Suzuki, K.2    Horie, H.3    Sugii, T.4
  • 25
    • 3643056433 scopus 로고
    • Theory of IGFET near and beyond pinch-off
    • J. A. Geurst, “Theory of IGFET near and beyond pinch-off,” Solid-State Electron., vol. 9, pp. 129-142, 1966.
    • (1966) Solid-State Electron. , vol.9 , pp. 129-142
    • Geurst, J.A.1
  • 26
    • 0017932965 scopus 로고
    • A charge sheet model of MOSFET
    • J. R. Brews, “A charge sheet model of MOSFET,” Solid-State Electron., vol. 21, pp. 345-355, 1978.
    • (1978) Solid-State Electron. , vol.21 , pp. 345-355
    • Brews, J.R.1
  • 27
    • 0021501347 scopus 로고
    • The effect of high fields on MOS device and circuit performance
    • C. G. Sodini, P. K. Ko, and J. L. Moll, “The effect of high fields on MOS device and circuit performance,” IEEE Trans. Electron Device, vol. ED-31, pp. 1386-1393, 1984.
    • (1984) IEEE Trans. Electron Device , vol.31 ED , pp. 1386-1393
    • Sodini, C.G.1    Ko, P.K.2    Moll, J.L.3
  • 28
    • 84916389355 scopus 로고
    • Large-signal analysis of a silicon diode oscillator
    • D. L. Scharfetter and H. K. Gummel, “Large-signal analysis of a silicon diode oscillator,” IEEE Trans. Electron Devices, vol. ED-16, pp. 64-77, 1969.
    • (1969) IEEE Trans. Electron Devices , vol.16 ED , pp. 64-77
    • Scharfetter, D.L.1    Gummel, H.K.2
  • 29
    • 0028545015 scopus 로고
    • Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's
    • T. Tosaka, K. Suzuki, and T. Sugii, “Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFET's,” IEEE Electron Device Lett., vol. 15, pp. 466-468, 1994.
    • (1994) IEEE Electron Device Lett. , vol.15 , pp. 466-468
    • Tosaka, T.1    Suzuki, K.2    Sugii, T.3
  • 30
    • 0024626928 scopus 로고
    • Analysis of conduction in fully depleted SOI MOSFET's
    • K. K. Young, “Analysis of conduction in fully depleted SOI MOSFET's,” IEEE Trans. Electron Devices, vol. 36, pp. 504-506, 1989.
    • (1989) IEEE Trans. Electron Devices , vol.36 , pp. 504-506
    • Young, K.K.1
  • 31
    • 0023596537 scopus 로고
    • Universal mobility-field curves for electrons and holes in MOS inversion layers
    • J. T. Watt and J. D. Plummer, “Universal mobility-field curves for electrons and holes in MOS inversion layers,” in 1987 Symp. VLSI Tech. Dig., pp. 81-82.
    • (1987) Symp. VLSI Tech. Dig. , pp. 81-82
    • Watt, J.T.1    Plummer, J.D.2
  • 32
    • 0024178927 scopus 로고
    • On the universality of inversion-layer mobility in n- and p-channel MOSFET's
    • S. Takagi, M. Iwase, and A. Toriumi, “On the universality of inversion-layer mobility in n- and p-channel MOSFET's,” in 1988 IEDM Tech. Dig., pp. 398-401.
    • (1988) IEDM Tech. Dig. , pp. 398-401
    • Takagi, S.1    Iwase, M.2    Toriumi, A.3
  • 34
    • 84939377322 scopus 로고
    • Effect of microscale thermal conduction on the packing limit of silicon-on insulator electronic devices
    • K. E. Goodson and M. I. Flik, “Effect of microscale thermal conduction on the packing limit of silicon-on insulator electronic devices,” IEEE Trans. Electron Devices, vol. 15, pp. 715-722, 1992.
    • (1992) IEEE Trans. Electron Devices , vol.15 , pp. 715-722
    • Goodson, K.E.1    Flik, M.I.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.