The Enhancement of Gate-Induced-Drain-Leakage (GIDL) Current in Short-Channel SOI MOSFET and its Application in Measuring Lateral Bipolar Current Gain β

IEEE Electron Device Letters

Volumn 13, Issue 11, 1992, Pages 572-574

  Chen, Jian ^a   Assaderaghi, Fariborz ^a   Ko, Ping Keung ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; ELECTRIC CURRENT MEASUREMENT; LEAKAGE CURRENTS; SILICON ON INSULATOR TECHNOLOGY; VLSI CIRCUITS;

GATE-INDUCED-DRAIN-LEAKAGE CURRENT; LATERAL BIPOLAR CURRENT; SHORT-CHANNEL SOI MOSFET;

MOSFET DEVICES;

EID: 0026954430     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.192844     Document Type: Article

References (9)

1. J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, and C. Hu, “Subbreak-down drain leakage current in MOSFET’s,” IEEE Electron Device Lett., vol. EDL-8, p. 515, 1987.
2. T. Y. Chan, J. Chen, P. K. Ko, and C. Hu, “The impact of gate-induced-drain-leakage on MOSFET scaling,” in IEDM Tech. Dig., Dec. 1987, p. 718.
3. C. Chang and J. Lien, “Corner-field induced drain leakage in thin oxide MOSFET’s,” in IEDM Tech. Dig., Dec. 1987, p. 714.
4. S. Veeraraghavan and J. G. Fossum, “Short channel effects in SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 36, p. 522, 1989.
5. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981.
6. K. K. Young and J. A. Burns, “Avalanche-induced drain-source breakdown in silicon-on-insulator n-MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp. 426, Apr. 1988.
7. J. S. T. Huang, J. S. Keung, and T. Fabian, “An analytical model for snapback in n-channel SOI MOSFET’s,” IEEE Trans. Electron Devices, vol. 38, pp. 2082, Sept. 1991.
8. J. M. Hwang, H. Lu, Y. D. Sheu, W. Bailey, P. Mei and G. Pollack, “Premature breakdown in non-fully depleted SOI/MOSFETs with body-tied-to-source structure,” in IEEE 1991 Int. SOI Conf. 1991, p. 34.
9. L. K. Wang et. al. “Enhanced performance of accumulation mode 0.5 μm CMOS/SOI operated at 300K and 85K,” in IEDM Tech. Dig., Dec. 1991, p. 679.