Nondestructive DCIV method to evaluate plasma charging damage in ultrathin gate oxides

IEEE Electron Device Letters

Volumn 20, Issue 5, 1999, Pages 238-240

  Guan, Hao ^a   Zhang, Yaohui ^b   Jie, B B ^a   He, Y D ^a   Li, Ming Fu ^a   Dong, Zhong ^c   Xie, Joseph ^b   Wang, J L F ^b   Yen, Andrew C ^b   Sheng, George T T ^b   Li, Weidan ^d  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

^c CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

^d AGERE SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC VARIABLES MEASUREMENT; MOS CAPACITORS; PLASMA INTERACTIONS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

DIRECT CURRENT VOLTAGE TECHNIQUE; PLASMA CHARGING DAMAGE; ULTRATHIN GATE OXIDES;

GATES (TRANSISTOR);

EID: 0032675338     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.761026     Document Type: Article

References (16)

1. J. P. McVittie, "Process charging in ULSI: Mechanisms, Impact and Solutions," in IEDM Tech. Dig., 1997 (invited paper).
2. F. Shone, K. Wu, J. Shaw, E. Hokelet, S. Mittal, and A. Haranahalli, "Gate oxide charging and elimination for metal antenna capacitor and transistor in VLSI CMOS double-layer metal technology," VLSI Technol., 1989, p. 73.
3. H. Shin, C. C. King, T. Horiuchi, and C. Hu, "Thin oxide charging current during plasma etching of aluminum," IEEE Electron Device Lett., vol. 12, p. 404, Aug. 1991.
4. A. Joshi, L. Chung, B. W. Min, and D. L. Kwong, "Gate oxide thickness dependence of RIE-induced damage on N-channel MOSFET reliability," in Int. Reliab. Phys. Symp., 1996, p. 300.
5. K. P. Cheung and C. P. Chang, "Plasma-charging damage: A physics model," J. Appl. Phys., vol. 75, p. 4415, 1994.
6. D. Park and C. Hu, "Plasma charging damage on ultrathin gate oxides," IEEE Electron Device Lett., vol. 19, p. 1, Jan. 1998.
7. H. C. Lin, C. C. Chen, C. H. Chien, S. K. Hsein, M. F. Wang, T. S. Chao, T. Y. Huang, and C. Y. Chang, "Evaluation of plasma charging in ultrathin gate oxides," IEEE Electron Device Lett., vol. 19, p. 68, Mar. 1998.
8. A. Neugroschel, C. T. Sah, K. M. Han, M. S. Carroll, T. Nishida, J. T. Kavalieros, and Y. Lu, "Direct-current measurements of oxide and traps on oxidized silicon," IEEE Trans. Electron Devices, vol. 42, p. 1657-1662, 1995.
9. A. Gupta, P. Fang, M. Song, M. R. Lin, D. Wollesen, K. Chen, and C. Hu, "Accurate determination of ultrathin gate oxide thickness and effective polysilicon doping of CMOS devices," IEEE Trans. Electron Device Lett., vol. 18, pp. 580-582, 1997.
10. B. B. Jie, M. F. Li, C. L. Lou, W. K. Chim, D. S. H. Chan, and K. F. Lo, "Investigation of interface traps in LDD pMOST's by the DCIV method," IEEE Electron Device Lett., vol. 18, p. 583, Dec. 1997.
11. W. Lukaszek, "Understanding and controlling wafer charging damage," Solid State Technol., June 1998, p. 101.
12. S. Fang, S. Murakawa, and J. P. McVittie, "Modeling of oxide breakdown from gate charging during resist ashing," IEEE Trans. Electron Devices, vol. 41, p. 1848, Oct. 1994.
13. S. Ma, J. P. McVittie, and K. C. Saraswat, "Prediction of plasma charging induced gate oxide damage by plasma charging probe," IEEE Electron Device Lett., vol. 18, p. 468, Oct. 1997.
14. C. H. Chien, C. Y. Chang, H. C. Lin, T. F. Chang, S. G. Chiou, L. P. Chen, and T. Y. Huang, "Resist-related damage on ultrathin gate oxide during ashing," IEEE Electron Device Lett., vol. 18, p. 33, 1997.
15. S. H. Lee, B. J. Cho, J. C. Kim, and S. H. Choi, "Quasibreakdown of ultrathin gate oxide under high field stress," in IEDM Tech. Dig., 1994, pp. 605-608.
16. B. E. Weir, P. J. Silverman, D. Monroe, K. S. Kirsch, M. A. Alam, G. B. Alers, T. W. Sorsch, G. L. Timp, F. Baumann, C. T. Liu, Y. Ma, and D. Hwang, "Ultrathin gate dielectrics: They break down, but do they fail?," in IEDM Tech. Dig., 1997, pp. 73-76. IEEE ELECTRON DEVICE LETTERS, VOL. 20, NO. 5, MAY 1999