A cost-effective design for testability: Clock line control and test generation using selective clocking

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 6, 1999, Pages 850-861

  Baeg, Sanghyeon ^a   Rogers, William A ^b  

^a CISCO SYSTEMS   (United States)

^b Austin Decisions Inc   (United States)

Author keywords

Clock line control; Design for testability (dft); Selective clocking

Indexed keywords

TIMING CIRCUITS; VECTORS;

CLOCK LINE CONTROL (CLC);

DESIGN FOR TESTABILITY;

EID: 0032674657     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.766732     Document Type: Article

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