Design for testability and test generation with two clocks

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1991, Pages 112-117

  Agrawal, V D ^a   Seth, S C ^b   Deogun, J S ^b  

^a LUCENT TECHNOLOGIES   (United States)

^b UNIVERSITY OF NEBRASKA LINCOLN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; FLIP FLOP CIRCUITS; VLSI CIRCUITS;

BINARY COUNTERS; EXPERIMENTAL VERIFICATION; NOVEL DESIGN; SEQUENTIAL ATPG; STORAGE ELEMENTS; SYNCHRONOUS CIRCUITS; TEST GENERATIONS; VECTOR SEQUENCES;

CLOCKS;

EID: 85013621402     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVD.1991.185102     Document Type: Conference Paper

References (12)

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