Delay fault models for VLSI circuits

Integration, the VLSI Journal

Volumn 26, Issue 1-2, 1998, Pages 21-40

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

Delay defects; Functional delay faults; Gate delay faults; Path delay faults; Transition faults

Indexed keywords

ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

FUNCTIONAL DELAY FAULTS; GATE DELAY FAULTS; PATH DELAY FAULTS;

VLSI CIRCUITS;

EID: 0032314930     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9260(98)00019-4     Document Type: Article

References (50)

1. P. Franco, E.J. McCluskey, Three-pattern tests for delay faults, Proc. 12th VLSI Test Symp., April 1994, pp. 452-456.
2. A. Pierzynska, S. Pilarski, Quality considerations delay fault testing, Proc. EURO-DAC 1995, September.
3. A. Pierzynska, S. Pilarski, Non-robust versus robust, Proc. Int. Test Conf., October 1995, pp. 123-131.
4. M. Sivaraman, A.J. Strojwas, Test vector generation for parametric path delay faults, Proc. Int. Test Conf., October 1995, pp. 132-138.
5. M. Sivaraman, A.J. Strojwas, A diagnosability metric for parametric path delay faults, Proc. 14th VLSI Test Symp., April 1996, pp. 316-322.
6. Z. Barzilai, B. Rosen, Comparison of AC self-testing procedures, Proc. Int. Test Conf., 1983, pp. 89-94.
7. J.L. Carter, V.S. Iyengar, B.K. Rosen, Efficient test coverage determination for delay faults, Proc. Int. Test Conf., September 1987, pp. 418-427.
8. K. Heragu, J.H. Patel, V.D. Agrawal, Segment delay faults: a new fault model, Proc. 14th VLSI Test Symp., April 1996, pp. 32-39.
9. I. Pomeranz, S.M. Reddy, J.H. Patel, On double transition faults as a delay fault model, Proc. Great Lakes Symp. on VLSI, March 1996, pp. 282-287.
10. G.L. Smith, Model for delay faults based upon paths, Proc. Int. Test Conf., 1985, pp. 342-349.
11. S.M. Reddy, M.K. Reddy, V.D. Agrawal, Robust tests for stuck-open faults in CMOS combinational logic circuits, Proc. 14th Int. Symp. on Fault-Tolerant Computing, June 1984, pp. 44-49.
12. E.S. Park, M.R. Mercer, Robust and nonrobust tests for path delay faults in combinational circuits, Proc. Int. Test Conf., September 1987, pp. 1027-1034.
13. K.-T. Cheng, H.-C. Chen, Generation of high quality non-robust tests for path delay faults, Proc. 31st Design Autom. Conf., June 1994, pp. 365-369.
14. L.-C. Chen, S.K. Gupta, M.A. Breuer, High quality robust tests for path delay faults, Proc. VLSI Test Symp., April 1997, pp. 88-93.
15. I. Pomernanz, S.M. Reddy, A generalized test generation procedure for path delay faults, Proc. 28th Fault-Tolerant Computing Symp., June 1998, pp. 274-283.
16. I. Pomernanz, S.M. Reddy, On testing delay faults in macro-based combinational circuits, Proc. Int. Conf. on Computer-Aided Design, November 1994, pp. 332-339.
17. I. Pomernanz, S.M. Reddy, Functional test generation for delay faults in combinational circuits, Proc. Int. Conf. on Computer-Aided Design, November 1995, pp. 687-694; also I. Pomernanz, S.M. Reddy, Functional test generation for delay faults in combinational circuits, ACM Trans. Design Automation, April 1998.
18. I. Pomernanz, S.M. Reddy, Functional test generation for delay faults in combinational circuits, Proc. Int. Conf. on Computer-Aided Design, November 1995, pp. 687-694; also I. Pomernanz, S.M. Reddy, Functional test generation for delay faults in combinational circuits, ACM Trans. Design Automation, April 1998.
19. B. Underwood, W.-O. Law, S. Kang, H. Konuk, Fastpath: a path- delay test generator for standard scan designs, Proc. Int. Test Conf., October 1994, pp. 154-163.
20. M. Abramovici, M. Breuer, A.D. Friedman, Digital Systems Testing and Testable Design, Computer Science Press, Rockville, MD, 1990.
21. H. Hengster, R. Drechsler, B. Becker, Testability properties of local circuit transformations with respect to the robust path-delay-fault model, Proc. 7th Int. Conf. on VLSI Design, January 1994, pp. 123-126.
22. H. Hengster, R. Drechsler, B. Becker, On local transformations and path delay fault testability, J. Electron. Testing - Theory Appl. (1995) 173-191.
23. A. Krstic, K.-T. Cheng, Resynthesis of combinational circuits for path count reduction and for path delay fault testability, Proc. Europ. Design & Test Conf., March 1996.
24. I. Pomeranz, S.M. Reddy, Design-for-testability for path delay faults in combinational circuits using test-points, 31st Design Autom. Conf., June 1994, pp. 358-364.
25. I. Pomeranz, S.M. Reddy, On synthesis-for-testability of combinational logic circuits, Proc. 32nd Design Autom. Conf., June 1995, pp. 126-132.
26. I. Pomeranz, S.M. Reddy, On the number of tests to detect all path delay faults in combinational logic circuits, IEEE Trans. Comput., 45 (1996) 50-62.
27. I. Pomeranz, S.M. Reddy, On cancelling the effects of logic sharing for improved path delay fault testability, Proc. Int. Test Conf., October 1996, pp. 357-366.
28. M. Yoeli, S. Rinon, Applications of ternary algebra to the study of static hazards, J. ACM (January 1964) 84-97
29. V.S. Iyenger, B.K. Rosen, J.A. Waicukauski, On computing the sizes of detected delay faults, IEEE Trans. Comput Aided Des. 9 (1990) 299-312.
30. A.K. Pramanick, S.M. Reddy, On the computation of the ranges of detected delay fault sizes, Proc. Int. Conf. on Computer-Aided Design, November 1989, pp. 126-129.
31. A.K. Pramanick, S.M. Reddy, On the detection of delay faults, Proc. Int. Test Conf., September 1988, pp. 680-687.
32. A.K. Pramanick, S.M. Reddy, On the fault coverage of delay fault detecting tests, Proc. Europ. Design Autom. Conf., March 1990, pp. 334-367.
33. V.S. Iyengar, G. Vijayan, Optimized test application timing for AC test, IEEE Trans. Comput. Aided Des. 11 (1992) 1439-1449.
34. W.-W. Mao, M.D. Ciletti, A variable observation time method for testing delay faults, Proc. 27th Design Autom. Conf., 1990, pp. 728-731.
35. J. Waicukauski, E. Lindbloom, B. Rosen V. Iyengar, Transition fault simulation, IEEE Des. Test 4 (1987) 32-38.
36. E.S. Park, B. Underwood, T.W. Williams, M.R. Mercer, Delay testing quality in timing optimized designs, Proc. Int. Test Conf., October 1991, pp. 897-905.
37. I. Pomeranz, S.M. Reddy, An efficient non-enumerative method to estimate path delay fault coverage, Proc. Int. Conf. on Computer-Aided Design, 1992, pp. 560-567.
38. C.J. Lin, S.M. Reddy, On delay fault testing in logic circuits, IEEE Trans. CAD (September 1987) 694-703.
39. W-N. Li, S.M. Reddy, S.K. Sahni, On path selection in combinational logic circuits, IEEE Trans. Comput. Aided Des. 8 (1989) 56-63.
40. I. Pomeranz, S.M. Reddy, P. Uppaluri, NEST: a non-enumerative test generation method for path delay faults in combinational circuits, Proc. 30th Design Autom. Conf., 1993, pp. 439-445.
41. D. Kagaris, S. Tragoudas, D. Karayiannis, Improved nonenumerative path-delay fault-coverage estimation based on optimal polynomial-time algorithms, IEEE Trans. Comput. Aided Des. 16 (1997) 309-315.
42. D. Karayiannis, S. Tragoudas, A nonenumerative ATPG for functionally sensitizable path delay faults, Proc. 16th VLSI Test Symp., April 1998, pp. 440-445.
43. K.-T. Cheng, H.-C. Chen, Delay testing for non-robust untestable circuits, Proc. Int. Test Conf., October 1993, pp. 954-961.
44. W.K. Lam, A. Saldanha, R.K. Brayton, A.L. Sangiovanni-Vincentelli, Delay fault-coverage and performance tradeoffs, Proc. 30th Design Autom. Conf., June 1993, pp. 446-451.
45. S. Kajihara, K. Kinoshita, I. Pomeranz, S.M. Reddy, A method for identifying robust dependent and functionally unsensitizable paths, proc. VLSI Design Conf., January 1997, pp. 82-87.
46. U. Sparmann, D. Luxenburger, K.-T. Cheng, S.M. Reddy, Fast identification of robust dependent path delay faults, Proc. 32nd Design Autom. Conf., June 1995.
47. W. Ke, P.R. Menon, Synthesis of delay-verifiable combinational circuits, IEEE Trans. Comput (1995) 213-222.
48. S.M. Reddy, C.J. Lin, S. Patil, An automatic test pattern generator for the detection of path delay faults, proc. Int. Conf. on Computer-Aided Design, November 1987, pp. 284-287.
49. M.H. Schultz, K. Fuchs, F. Fink, Advanced automatic test pattern generation techniques for path delay faults, Proc. Int. Symp. on Fault-Tolerant Computing, June 1989, pp. 44-51.
50. J. Rajski, H. Cox, A method to calculate necessary assignments in algorithmic test pattern generation, Proc. Int. Test Conf., 1990, pp. 25-34.