Resynthesis of combinational circuits for path count reduction and for path delay fault testability

Proceedings of European Design and Test Conference

Volumn , Issue , 1996, Pages 486-490

  Krstic, Angela ^a   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; FAILURE ANALYSIS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL MODELS;

PATH COUNT REDUCTION; PATH DELAY FAULT TESTABILITY;

COMBINATORIAL CIRCUITS;

EID: 0029756563     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)