A generalized test generation procedure for path delay faults

Digest of Papers - 28th Annual International Symposium on Fault-Tolerant Computing, FTCS 1998

Volumn 1998-January, Issue , 1998, Pages 274-283

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a University of Iowa   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC FAULT CURRENTS; FAULT TOLERANCE;

ACCURATE MODELING; LARGE CIRCUITS; MULTIPLE TEST; PATH DELAY FAULT; TEST GENERATION PROCEDURE; TEST GENERATIONS; WORSTCASE;

TESTING;

EID: 85043376539     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FTCS.1998.689478     Document Type: Conference Paper

References (12)

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