Design methodology and optimization of gate-driven NMOS BSD protection circuits in submicron CMOS processes

IEEE Transactions on Electron Devices

Volumn 45, Issue 12, 1998, Pages 2448-2456

  Chen, Julian Zhiliang ^a   Amerasekera, E A ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; ELECTRIC DISCHARGES; ELECTROSTATICS; GATES (TRANSISTOR); OPTIMIZATION;

ELECTROSTATIC DISCHARGES; NMOS DEVICES;

MOS DEVICES;

EID: 0032306570     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.735721     Document Type: Article

References (15)

1. K-L. Chen, The effects of interconnect process and snapback voltage on the ESD failure threshold of NMOS transistors," IEEE Trans. Electron Devices, vol. 35, p. 2140, Dec. 1988.
2. T. Polgreen and A. Chatterjee, Improving the ESD failure threshold of silicided ra-MOS output transistors by ensuring uniform current flow," IEEE Trans. Electron Devices, vol. 39, p. 379, Feb. 1992.
3. A. Amerasekera, V. McNeil, and M. Rodder, Correlating drain junction scaling, salicide thickness, and lateral NPN behavior, with the ESD/EOS performance of a 0.25 /j,m CMOS process," in IEDM Tech. Dig., 1996, pp. 318.
4. A. Amerasekera and C. Duvvury, The impact of technology scaling on ESD robustness and protection circuit design," in Proc. 16th EOS/ESD Symp., 1994, p. 237.
5. C. H. Diaz, T. E. Kopley, and P. J. Marcous, Building-in ESD/EOS reliability for sub-halfmicron CMOS processes," IEEE Trans. Electron Devices, vol. 43, p. 991, June 1996.
6. C. Duvvury and C. H. Diaz, Dynamic gate coupling of NMOS for efficient output ESD protection," in Proc. IRPS, 1992, p. 141.
7. D. Krakauer and K. Mistry, ESD protection in a 3.3 V sub-micron suicided CMOS technology," in Proc. 14th EOS/ESD Symp., 1992, p. 250.
8. D. Krakauer, K. Mistry, and H. Partovi, Circuit interactions during electrostatic discharge," in Proc. 16th EOS/ESD Symp., 1994, p. 113.
9. S. Ramaswamy, C. Duvvury, and S.-M. Kang, EOS/ESD reliability of deep sub-micron NMOS protection devices," in Proc. IRPS, 1995, p. 284.
10. A. Amerasekera, C. Duvvury, V. Reddy, and M. Rodder, Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes," in IEDM TEch. Dig., 1995, p. 547.
11. J. Z. Chen, A. Amerasekera, and T. Vrotsos, Bipolar SCR ESD protection circuit for high speed submicron bipolar/BiCMOS circuits," in IEDM Tech. Dig., 1995, p. 337.
12. J. Z. Chen, X. Y. Zhang, A. Amerasekera, and T. Vrotsos, Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits," in Proc. IRPS, 1996, p. 227.
13. T. J. Maloney and S. Dabral, Novel clamp circuits for 1C power supply protection," in Proc. 17th EOS/ESD Symp., 1995, p. 1.
14. A. Amerasekera, S. Ramaswamy, M.-C. Chang, and C. Duvvury, Modeling MOS snapback and parasitic bipolar action for circuit-level ESD and high current simulations," in Proc. IRPS, 1996, p. 318.
15. 77 SPICES User'sand Reference Manual, Texas Instruments, Inc., 1996.