Correlating Drain Junction Scaling, Salicide Thickness, and Lateral NPN Behavior, with the ESD/EOS Performance of a 0.25 pm ClLlOS Process.

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 893-896

  Amerasekera, Ajith ^a   McNeil, Vincent ^a   Raldder, Mark ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ECONOMIC AND SOCIAL EFFECTS; CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR JUNCTIONS; SUBSTRATES; TRANSISTORS;

CURRENT GAINS; DIRECT METHOD; DRAIN JUNCTIONS; ESD PERFORMANCE; JUNCTION DEPTH; NPN TRANSISTOR; PERFORMANCE; SALICIDES; SCALINGS; SELF-BIASED;

ELECTROSTATIC DEVICES; INTEGRATED CIRCUIT MANUFACTURE;

CURRENT GAIN; DRAIN SOURCE DIFFUSION DEPTH; ELECTRICAL OVERSTRESS DAMAGE; ELECTROSTATIC DISCHARGE; SALICIDE THICKNESS;

EID: 0030421382     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554123     Document Type: Conference Paper

References (7)

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3. A.Amerasekera, C.Duvvury, V.Reddy, M.Rodder, in Tech. Dig. IEDM, 547, 1995.
4. C.Diaz, T.Kopley, P.Marcoux, IEEE T~ans. Elec. Dew., ED-43, 991, 1996.
5. H.Ishizuka, K.Okuyama, K.Kubota, PFOC. 38nd IRPS, 286, 1994.
6. A.Amerasekera, J.Seitchik, Tech. Dig. IEDM, 455,1994.
7. A.Amerasekera, S.Aamaswamy, M.-C.Chang, C.Duvvury, Proc. 34th IRPS, 318, 1996.