Design and layout of a high ESD performance NPN structure for submicron BiCMOS/bipolar circuits

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 1996, Pages 227-232

  Chen, Julian Z ^a   Zhang, Xin Yi ^a   Amerasekera, Ajith ^a   Vrotsos, Tom ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; BIPOLAR SEMICONDUCTOR DEVICES; INTEGRATED CIRCUIT MANUFACTURE; OVERCURRENT PROTECTION; OVERVOLTAGE PROTECTION; SEMICONDUCTOR DEVICE STRUCTURES; ZENER DIODES;

OPTIMAL PROTECTION STRUCTURE; SPECIFIC MULTI-EMITTER LAYOUT TECHNIQUE; ZENER TRIGGER CIRCUIT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0029705786     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/relphy.1996.492124     Document Type: Conference Paper

References (8)