Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1995, Pages 547-550

  Amerasekera, Ajith ^a   Duvvury, Charvaka ^a   Reddy, Vijay ^a   Rodder, Mark ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; ELECTRIC DISCHARGES; ELECTROSTATICS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; PERFORMANCE; PROTECTION; SUBSTRATES;

ELECTROSTATIC DISCHARGE PROTECTION; PROTECTION CIRCUIT DESIGN; SALICIDES; SUBSTRATE TRIGGERING;

CMOS INTEGRATED CIRCUITS;

EID: 0029489170     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)