Special ATPG to correlate test patterns for low-overhead mixed-mode BIST

Proceedings of the Asian Test Symposium

Volumn , Issue , 1998, Pages 492-499

  Karkala, Madhavi ^a   Touba, Nur A ^a   Wunderlich, Hans Joachim ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST PATTERN GENERATORS (ATPG); LOW-OVERHEAD MIXED-MODE BUILT-IN SELF TEST (BIST);

CORRELATION METHODS; ELECTRIC FAULT LOCATION; ENCODING (SYMBOLS); INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; RANDOM PROCESSES;

BUILT-IN SELF TEST;

EID: 0032299170     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (35)

1. Aboulhamid, M.E., and E. Cerny, "A Class of Test Generators for Built-in Testing," IEEE Transactions on Computers , Vol. C-32, No. 10, pp. 957-959, Oct. 1983.
2. AlShaibi, M.F., and CR. Kirne, "Fixed-Biased Pseudorandom Built-in Self-Test for Random Pattern Resistant Circuits," Proc. of International Test Conference, pp. 929-938, 1994.
3. AlShaibi, M.F., and CR. Kirne, "MFBIST: A BIST Method for Random Pattern Resistant Circuits," Proc. of International Test Conf, pp. 176-185, 1996.
4. Agarwal, V.K., and E. Cerny, "Store and Generate Built-in Testing Approach," Proc. of FTCS-17, pp. 35-40, 1981.
5. Akers, S.B., and W. Jansz, "Test Set Embedding in a Built-in Self-Test Environment," Proc. of International Test Conference, pp. 257-263, 1989.
6. Chatterjee, M., and D.K. Pradhan, "A Novel Pattern Generator for Near-Perfect Fault Coverage," Proc. of VLSI Test Symposium, pp. 417-425, 1995.
7. Daehn, W., and J. Muncha, "Hardware Test Pattern Generation for Built-in Testing," Proc. of International Test Conference, pp. 110-113, 1981.
8. Dandapani, R., J. Patel, and J. Abraham, "Design of Test Pattern Generators for Built-in Test," Proc. of International Test Conf, pp. 315-319, 1984.
9. Dufaza, C, and G. Cambon, "LFSR based Deterministic and Pseudo-Random Test Pattern Generator Structures," Proc. of European Test Conference, pp. 27-34, 1991.
10. Dufaza, C, C. Chevalier, and L.F.C. Lew Yan Voon, "LFSROM: A Hardware Test Pattern Generator for Deterministic ISCAS85 Test Sets," Proc. of Asian Test Symposium, pp. 160-165, 1993.
11. Dufaza, C, H. Viallon, and C. Chevalier, "BIST Hardware Generator for Mixed Testing Scheme," Proc. of European Design & Test Conf, pp. 424-430, 1995.
12. Edirisooriya, G., and J.P. Robinson, "Design of Low Cost ROM Based Test Generators," Proc. of VLSI Test Symposium, pp. 61-66, 1992.
13. Eichelberger, E.B., and E. Lindbloom, "Random-Pattern Coverage Enhancement and Diagnosis for LSSD Logic Self-Test," IBM Journal of Research and Dev., Vol. 27, No. 3, pp. 265-272, May 1983.
14. Goel, P., and B.C. Rosales, "Test Generation and Dynamic Compaction of Tests," Proc. of International Test Conference, pp. 189-192, 1979.
15. Goel, P., "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuks," IEEE Transactions on Computers, Vol. C-30, No. 3, pp. 215-222, Mar. 1981.
16. Heilebrand, S., S. Tarnick, J. Rajski, and B. Courtois, "Generation of Vector Patterns Through Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," Proc. of International Test Conference, pp. 120-129, 1992.
17. Hellebrand, S., J. Rajski, S. Tarnick, S. Venkataraman and B. Courtois, "Built-in Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Trans. Comput., Vol. 44, No. 2, pp. 223-233, Feb. 1995.
18. Hellebrand, S., B. Reeb, S. Tarnick, and H.-J. Wunderlich, "Pattern Generation for a Deterministic BIST Scheme," Proc. of International Conference on Computer-Aided Design (ICCAD), 1995.
19. Kajihara, S., I. Pomeranz, K. Kinoshita, S.M. Reddy, "Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits," Proc. of the 30th Design Automation Conference, pp. 102-106, 1993.
20. Kangaris, D., S. Tragoudas, A. Majumdar, "Deterministic Test Set Reproduction by a Counter," Proc. ofEurop. Design & Test Conf, pp. 37-41, 1996.
21. Kangaris, D., and S. Tragoudas, "Generating Deterministic Unordered Test Patterns with Counter," Proc. of VLSI Test Symposium, pp. 374-379, 1996.
22. Kiefer, G., and H.-J. Wunderlich, "Using BIST Control for Pattern Generation," Proc. of International Test Conference, 1997.
23. Koenemann, B., "LFSR-Coded Test Patterns for Scan Designs," Proc. of European Test Conference, pp. 237-242, 1991.
24. Pateras, S., and J. Rajski, "Cube-Contained Random Patterns and Their Application to Complete Testing of Synthesized Multi-level Circuits," Proc. of international Test Conference, pp. 473-482, 1991.
25. Pomeranz, 1., and S.M. Reddy, "3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set for Combinational and Sequential Circuits," IEEE Trans, on Computer-Aided Design, Vol. 12, No. 7, pp. 1050-1058, Jul. 1993.
26. Pomeranz, L, L.N. Reddy, and S.M. Reddy, "COMPACTEST: A Method to Generate Compact Test Sets for Combinational Circuits," IEEE Transactions on Computer-Aided Design, Vol. 12, No. 7, pp. 1040-1049, Jul. 1993.
27. Reeb, B., H.-J. Wunderlich, "Deterministic Pattern Generation for Weighted Random Pattern Testing," Proc. of European Design & Test Conference, pp. 30-36, 1996.
28. Touba, N.A., and E.J. McCluskey, "Transformed Pseudo-Random Patterns for BIST," Proc. of VLSI Test Symposium, pp. 410-416, 1995.
29. Touba, N.A., and E.J. McCluskey, "Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST," Proc. of International Test Conference, pp. 674-682, 1995.
30. Touba, N.A., and E.J. McCluskey, "Altering a Pseudo-Random Bit Sequence for Scan-Based BIST," Proc. of International Test Conf, pp. 167-175, 1996.
31. Tromp, G., "Minimal Test Sets for Combinational Circuits," Proc. of International Test Conference, pp. 204-209, 1991.
32. Venkataraman, S., J. Rajski, S. Hellebrand, and S. Tarnick, "An Efficient BIST Scheme Based on Reseeding of Multiple Polynomial Linear Feedback Shift Registers," Proc. of Int. Conf. on Computer-Aided Design (ICCAD), pp. 572-577, 1993.
33. Wunderlich, H.-J., and G. Kiefer, "Bit-Flipping BIST," Proc. of International Conference on Computer-Aided Design (ICCAD), 1996.
34. Zacharia, N., J. Rajski, and J. Tyszer, "Decompression of Test Data Using Variable-Length Seed LFSRs," Proc. VLSI Test Sym., pp. 426-433, 1995.
35. Zacharia, N., J. Rajski, J. Tyszer, and J.A. Waicukauski, "Two-Dimensional Test Data Decompressor for Multiple Scan Designs," Proc. of International Test Conference, pp. 186-194, 1996.