Generating deterministic unordered test patterns with counters

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1996, Pages 374-379

  Kagaris, Dimitrios ^a   Tragoudas, Spyros ^a  

^a SOUTHERN ILLINOIS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COUNTING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MATRIX ALGEBRA; VECTORS;

BUILT IN SELF TEST; COUNTER BASED SCHEMES; DETERMINISTIC TEST PATTERN GENERATION; UNORDERED TEST PATTERNS;

INTEGRATED CIRCUIT TESTING;

EID: 0029713988     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)