Impact of Epi facets on deep submicron elevated source/drain MOSFET characteristics

IEEE Transactions on Electron Devices

Volumn 45, Issue 6, 1998, Pages 1377-1380

  Sun Jie, J ^a   Osburn, Carlton M ^b  

^a North Carolina State University   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Elevated source drain; Epi facet; MOSFET

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC RESISTANCE; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR JUNCTIONS;

DRAIN INDUCED BARRIER LOWERING (DIBL);

MOSFET DEVICES;

EID: 0032095688     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.678583     Document Type: Article

References (17)

1. M. Ono, M. Saito, T. Yoshimoto, C. Fiegna, T. Ohguro, and H. Iwai, Sub-50-nm gate length N-MOSFET with 10-nm phosphorous source and drain junctions, in IEDM Tech. Dig., 1993, p. 119.
2. Y. Taur, S. Wind, Y. J. Mii, D. Moy, K. A. Jenkins, C. L. Chen, P. J. Coane, D. Klaus, J. Bucchignano, M. Rosenfield, M. G. R. Thomson, and M. Polcari, High-performance 0.1-μm CMOS devices with 1.5 V power supply, in IEDM Tech. Dig., 1993, p. 127.
3. K. F. Lee, R. H. Yan, D. Y. Jeon, G. M. Chin, Y. O. Kim, D. M. Tennant, B. Razavi, H. D. Lin, Y. G. Wey, E. H. Westerwick, M. D. Morris, R. W. Johnson, T. M. Liu, M. Tarsia, M. Cerullo, R. G. Swartz, and A. Ourmazd, Room temperature O.I-ftm CMOS technology with 11.8 ps gate delay, in IEDM Tech. Dig., 1993, p. 131.
4. H. Hu, L. T. Su, I. Y. Yang, D. A. Antoniadis, and H. I. Smith, Channel and source/drain engineering in high-performance sub-0.1-μm NMOSFET using X-ray lithography, in Proc. Symp. VLSI Technol., 1994, p. 17.
5. S. Wong, D. Bradbury, D. Chen, and K. Chiu, Elevated source/drain MOSFET, in IEDM Tech. Dig., 1984, p. 634.
6. +n junction utilizing selective silicon growth and rapid thermal annealing, in IEDM Tech. Dig., 1987, p. 590.
7. J. R. Pfiester, R. D. Sivan, H. M. Liaw, C. A. Seelbach, and C. D. Gunderson, A self-aligned elevated source/drain MOSFET, IEEE Electron Device Lett., vol. 11, p. 365, Sept. 1990.
8. J. Y. Tsai, J. Sun, K. F. Yee, and C. M. Osburn, DIBL considerations of extended drain structure for 0. l-μm MOSFET's, IEEE Electron Device Lett., vol. 17, p. 331, July 1996.
9. J. J. Sun, J. Y. Tsai, K. F. Yee, and C. M. Osburn, The use of elevated source/drain in sub-0.1-μm NMOSFET's, in SPIE's Proc. Microelectronic Device and Multilevel Interconnection Technology II, 1996, vol. 2875, p. 178.
10. C. Mazure, J. Fitch, and C. Gunderson, Facet engineered elevated source/drain by selective Si epitaxy for 0.35-μm MOSFET's, in IEDM Tech. Dig., 1992, p. 853.
11. M. Rodder and D. Yeakley, Raised source/drain MOSFET with dual sidewall spacers, IEEE Electron Device Lett., vol. 12, p. 89, Mar. 1991.
12. K. Weldon, T. Dory, C.-H. Jan, B. Eandau, A. Stivers, and M. Bohr, Raised source-drains using selective silicon deposition for sub-half micron CMOS devices, in Ext. Abst. ECS Meeting, Fall 1994, p. 756.
13. Y. Nakahara, K. Takeuchi, T. Tatsumi, Y. Ochiai, S. Manako, S. Samukawa, and A. Furukawa, Ultra-shallow in-situ-doped raised source/drain structure for sub-tenth micron CMOS, in VLSI Symp. Tech. Dig., 1996, p. 174.
14. D. A. Antoniadis and J. E. Chung, Physics and technology of ultrashort-channel MOSFET devices, in IEDM Tech. Dig., 1991, p. 21.
15. Y. Ohkura, Quantum effects in Si n-MOS inversion layer at high substrate concentration, Solid State Electron., vol. 33, p. 1581, 1990.
16. M. J. Van Dort, P. H. Woerlee, A. J. Walker, C. A. H. Juffermans, and H. Eifka, Influence of high substrate doping level on the threshold voltage and the mobility of deep submicrometer MOSFET's, IEEE Trans. Electron Devices, vol. 39, p. 932, Apr. 1992.
17. C. H. Wang, Identification and measurement of scaling-dependent parasitic capacitances of small-geometry MOSFET's, IEEE Trans. Electron Devices, vol. 43, p. 965, June 1996.