Identification and measurement of scaling-dependent parasitic capacitances of small-geometry MOSFET's

IEEE Transactions on Electron Devices

Volumn 43, Issue 6, 1996, Pages 965-972

  Wang, Chih Hsin ^a,b  

^a MOTOROLA INC   (United States)

^b Rockwell Semiconductor Systems   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MEASUREMENT; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; GATES (TRANSISTOR); MATHEMATICAL MODELS; NUMERICAL METHODS;

GATE LENGTHS; GATE TO SOURCE CAPACITANCE; INVERTER GATE DELAY;

MOSFET DEVICES;

EID: 0030173665     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.502131     Document Type: Article

References (5)

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2. [2J B. J. Sheu and P. K. Ko, A capacitance method to determine channel lengths for conventional and LDD MOSFET's, IEEE Electron Device Lett., vol. EDL-5, pp. 491-493. 1984.
3. [3j J.-C. Guo, S. S.-S. Chung, and C. C.-H. Hsu, A new approach to determine the effective channel length and the drain-and-source aeries resistance of miniaturized MOSFET's, tEEE Trans. Electron Devices, vol. 41, pp. 1811-1818, 1994.
4. [£] S.-W. Lee. A capacitance-based method for experimental determination of metallurgical channel length of submicron LDD MOSFET's, IEEE Trans. Electron Devices, vol. 41. pp. 403-4112, 1994.
5. A. Cetner. K. Iniewski, and A. Jakubowski, A simple formula for 2-D capacitance, Solid-State Electronics, vol. 31, pp. 973-974, 1988.