Raised Source/Drain MOSFET with Dual Sidewall Spacers

IEEE Electron Device Letters

Volumn 12, Issue 3, 1991, Pages 89-91

  Rodder, Mark ^a   Yeakley, D ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTALS - EPITAXIAL GROWTH; SEMICONDUCTING SILICON - DOPING;

MOSFET DUAL SIDEWALL SPACERS; RAISED SOURCE/DRAIN MOSFET;

SEMICONDUCTOR DEVICES, MOSFET;

EID: 0026116570     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.75721     Document Type: Article

References (7)

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2. H. Shibata, Y. Suizu, S. Samata, T. Matsuno, and K. Hashimoto, “High performance half-micron PMOSFET’s with 0.1 µm shallow p + n junction utilizing selective silicon growth and rapid thermal annealing,” in IEDM Tech. Dig., Dec. 1987, p. 590.
3. J. R. Pfiester, R. D. Sivan, H. M. Liaw, C. A. Seelbach, and C. D. Gunderson, “A self-aligned elevated source/drain MOSFET,” IEEE Electron Device Lett., vol. 11, no. 9, p. 365, Sept. 1990.
4. A. Ishitani, H. Kitajima, N. Endo, and N. Kasai, “Facet formation in selective silicon epitaxial growth,” Japan. J. Appl. Phys., vol. 24, no. 10, p. 1267, Oct. 1985.
5. R. A. Chapman et al., “An 0.8 µm CMOS technology for high performance logic applications,” in IEDM Tech. Dig., Dec. 1987, p. 362.
6. A. F. Tasch, H. Shin, and C. M. Maziar, “A new structural approach for reducing hot carrier generation in deep submicron MOSFET’s,” in Symp. VLSI Technology, 1990, p. 43.
7. R. A. Chapman et al., “Submicron BiCMOS well design for optimum circuit performance,” in IEDM Tech. Dig., Dec. 1988, p. 756.