Optimal clock period clustering for sequential circuits with retiming

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 17, Issue 6, 1998, Pages 489-498

  Pan, Reichen ^a   Karandikar, Arvind K ^a   Liu, C L ^a  

^a Clarkson University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DELAY CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; SEQUENTIAL CIRCUITS;

CIRCUIT CLUSTERING;

VLSI CIRCUITS;

EID: 0032093080     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.703830     Document Type: Article

References (29)

1. N. Sherwani Algorithms for VLSI Physical Design Automation. Nor well MA: Kluwer 1995.
2. C. J. Alpert and A. B. Kahng Recent directions in netlist partitioning A survey Integr. VLSIJ.. vol. 19 pp. 1-81 1995.
3. F. M. Johannes Partitioning of VLSI circuits and systems i ACM/IEEE Design Automation Conf. (DAC). 1996 pp. 83-87.
4. C. J. Alpert and S.-Z. Yao Spectral partitioning: The more eigenvector the better in ACM/IEEE Design Automation Conf. (DAC) 1995 pp 195-200.
5. J. Cong Z. Li and R. Bagrodia Acyclic multi-way partitioning o boolean networks in ACM/IEEE Design Automation Conf. (DAC) 1994. pp. 670-675.
6. P. K. Chan M. D. F. Schlag and J. Y. Zien Spectral based multi-way FPGA partitioning in Int. Symp. Field-Programmable Gate Arrays 1995. pp. 133-139.
7. D. Cheng C.-C. Lin and M. Marek-Sadowska Circuit partitionin with logic perturbation in Int. Conf. on Computer-Aided Design (IC CAD) 1995 pp. 650-655.
8. S. Dutt and W. Deng A probability-based approach to VLSI circui partitioning in ACM/IEEE Design Automation Conf. (DAC) 1996 pp 100-105.
9. C. Fiduccia and R. Matheyses A linear-time heuristic for improvin network partitions in ACM/IEEE Design Automation Conf. (DAC) 1982 pp. 175-181.
10. L. W. Hagen D. J.-H. Huang and A. B. Kahng On implementatio choices for iterative improvement partitioning algorithms in Europea Design Automation Conf. 1995 pp. 144-149.
11. S. Hauck and G. Borriello An evaluation of bipartitioning techniques in Chapel Hill Conf. Advanced Research VLSI 1995 pp. 383-402.
12. L. J. Hwang and A. E. Gamal Min-cut replication in partitione networks IEEE Trans. Computer-Aided Design vol. 14 pp. 96-106 1995.
13. C. Kring and A. Newton A cell-replicating approach to min-cut-base circuit partitioning in Int. Conf. Computer-Aided Design (ICCAD) 1991 pp. 2-5.
14. K. Roy-Neogi and C. Sechen Partitioning with performance optimization in Int. Symp. Field-Programmable Gate Arrays 1995 pp 146-152.
15. M. Shih and E. S. Kuh Circuit partitioning under capacity and I/ constraints in Custom Integrated Circuits Conf. 1994 pp. 659-662.
16. H. Vaishnav and M. Pedram Delay optimal partitioning targeting lo power VLSI circuits in Int. Conf. Computer-Aided Design (ICCAD) 1995 pp. 638-643.
17. H. Yang and D. Wong New algorithms for min-cut replication i partitioned circuits in Int. Conf. Computer-Aided Design (ICCAD) 1995 pp. 216-223.
18. C.-W. Yeh C.-K. Cheng and T.-T. Y. Lin Circuit clustering using stochastic flow injection method IEEE Trans. Computer-Aided Design vol. 14 pp. 154-162 1995.
19. R. Murgai R. Brayton and A. Sangiovanni-Vincentelli On clustering for minimum delay/area in Int. Conf. Computer-Aided Desig (ICCAD) 1991 pp. 6-9.
20. E. Lawler K. Levitt and J. Turner Module clustering to minimiz delay in digital networks IEEE Trans. Comput. vol. 18 pp. 47-57 1969.
21. R. Rajaraman and D. Wong Optimal clustering for delay minimization in ACM/IEEE Design Automation Conf. (DAC) 1993 pp 309-314.
22. C. E. Leiserson and J. B. Saxe Retiming synchronous circuitry Algorithmica vol. 6 pp. 5-35 1991.
23. N. V. Shenoy and R. Rudell Efficient implementation of retiming i Int. Conf. Computer-Aided Design (ICCAD) 1994 pp. 226-233.
24. R. B. Deokar and S. S. Sapatnekar A fresh look at retiming via cloc skew optimization in ACM/IEEE Design Automation Conf. (DAC) 1995 pp. 310-315.
25. P. Pan Continuous retiming: algorithms and applications in Int. Conf on Computer Design (ICCD) 1997 pp. 116-121.
26. L.-T. Liu M. Shih N. Chou C.-K. Cheng and W. Ku Performancedriven partitioning using retiming and replication in Int. Conf. o Computer-Aided Design (ICCAD) pp. 296-299 1993.
27. L.-T. Liu M.-T. Kuo C.-K. Cheng and T. Hu Performance-drive partitioning using a replication graph approach in ACM/IEEE Desig Automation Conf. (DAC) 1995 pp. 206-210.
28. P. Pan and C. L. Liu Optimal clock period FPGA technology mappin for sequential circuits in ACM/IEEE Design Automation Conf. (DAC) pp. 720-725 1996.
29. T. H. Cormen C. E. Leiserson and R. L. Rivest Introduction t Algorithms. New York: McGraw-Hill 1990.