Fresh look at retiming via clock skew optimization

Proceedings - Design Automation Conference

Volumn , Issue , 1995, Pages 310-315

  Deokar, Rahul B ^a   Sapatnekar, Sachin S ^a  

^a IOWA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; LOGIC DESIGN; LOGIC GATES; TIMING CIRCUITS; VLSI CIRCUITS;

CLOCK DISTRIBUTION NETWORK; CLOCK SKEW; CLOCK SKEW OPTIMIZATION; EDGE TRIGGERED FLIP FLOP; RETIMING;

FLIP FLOP CIRCUITS;

EID: 0029233969     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)