Min-Cut Replication in Partitioned Networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 14, Issue 1, 1995, Pages 96-106

  Hwang, L James ^a   Gamal, Abbas El ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; ELECTRIC NETWORK SYNTHESIS; GRAPH THEORY; HEURISTIC METHODS; POLYNOMIALS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGAS); MIN CUT REPLICATION; PARTITIONED NETWORKS; PIN CONSTRAINT; POLYNOMIAL TIME ALGORITHMS;

LOGIC CIRCUITS;

EID: 0029209611     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.363121     Document Type: Article

References (17)

1. R. K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang, “MIS: A multiple-level logic optimization system,” IEEE Trans. Computer-Aided Design, vol. 6, no. 6, pg. 1062–1081, Nov. 1987.
2. C. M. Fiduccia and R. M. Mattheyses, “A linear time heuristic for improving network partitions,” in Proc. 19th Design Automation Conf., 1982, pp. 175–181.
3. A. El Gamal et al., “Architectures, circuits and computer-aided design for electrically programmable VLSI,” Semi-Annual Tech. Report, Defense Advanced Research Projects Agency, Mar. 1991.
4. M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness. New York: Freeman, 1979.
5. A. V. Goldberg and R. E. Tarjan, “A new approach to the maximum flow problem,” in Proc. 18th ACM Symp. Theory Comput., pp. 136–146, 1986.
6. T. C. Hu and K. Moerder, “Multiterminal flows in a hypergraph,” in VLSI Circuit Layout: Theory and Design, T. C. Hu and E. S. Kuh, Eds., New York: IEEE Press, pp. 87–93.
7. L. J. Hwang, “Replication in partitioned networks,” Ph.D. dissertation, Stanford Univ., 1994.
8. J. Hwang and A. El Gamal, “Optimal replication for min-cut partitioning,” in Dig. Tech. Papers, ICCAD-92, pp. 432–435, IEEE and ACM, 1992.
9. B. W. Kernighan and S. Lin, “An efficient heuristic procedure for partitioning graphs,” The Bell Sys. Tech. J., vol. 49, pp. 291–307, 1970.
10. C. Kring and A. R. Newton, “A cell-replicating approach to mincut-based circuit partitioning,” in Dig. Tech. Papers, ICCAD-91, pp. 2–5, 1991.
11. L. R. Ford, Jr. and D. R. Fulkerson, Flows In Networks. Princeton, NJ: Princeton Univ. Press, 1962.
12. S. Lan, A. Ziv, and A. El Gamal, “Routing algorithms for field programmable multi-chip modules,” in Proc. 31st Design Automation Conf., IEEE and ACM, 1994.
13. T. Lengauer, Combinatorial Algorithms for Integrated Circuit Layout. Sussex, UK: Wiley, 1990.
14. W. A. Notz, E. Schischa, J. L. Smith, and M. G. Smith, “Benefitting the system designer,” Electronics, pp. 130–141, Feb. 1967.
15. R. Rajaraman and D. F. M. Wong, “Optimal clustering for delay minimization,” in Proc. 30th Design Automation Conf., 1993, pp. 309–314.
16. R. L. Russo, P. H. Oden, and P. K. Wolff, Sr., “A heuristic procedure for the partitioning and mapping of computer logic graphs,” IEEE Trans. Comput., vol. 20, no. 12, pp. 1455–1462, Dec. 1971.
17. S. Walters, “Computer-aided prototyping for ASIC-based systems,” IEEE Design Test Comp., pp. 4–10, June 1991.