Circuit partitioning with logic perturbation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 650-655

  Cheng, David Ihsin ^a   Lin, Chih Chang ^a   Marek Sadowska, Malgorzata ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; GRAPH THEORY; LOGIC DESIGN; MATHEMATICAL MODELS; OPTIMIZATION; PERTURBATION TECHNIQUES;

ALTERNATIVE WIRES; CIRCUIT PARTITIONING; LOGIC PERTURBATION;

LOGIC CIRCUITS;

EID: 0029512559     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (20)