Delay optimal partitioning targeting low power VLSI circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1995, Pages 638-643

  Vaishnav, Hirendu ^a   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; OPTIMIZATION;

CIRCUIT PARTITIONING; DELAY OPTIMAL PARTITIONING; LAWLER'S CLUSTERING ALGORITHM;

VLSI CIRCUITS;

EID: 0029516113     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)