Fast Conversion Techniques for Binary-Residue Number Systems

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 41, Issue 12, 1994, Pages 927-929

  Vinnakota, Bapiraju ^a   Bapeswara Rao, V V ^b  

^a UNIVERSITY OF MINNESOTA   (United States)

^b NORTH DAKOTA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; MICROPROCESSOR CHIPS;

BINARY RESIDUE NUMBER SYSTEMS; FAST CONVERSION TECHNIQUES;

NUMBER THEORY;

EID: 0028751974     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.340862     Document Type: Article

References (6)

1. M. A. Soderstrand, W. K. Jenkins, G. A. Julien, and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Signal Processing. New York: IEEE Press, 1986.
2. F. D. Taylor and A. S. Ramanarayanan, “An efficient residue-to-binary converter,” IEEE Trans. Circuits Syst., vol. CAS-28, no. 12, pp. 1164-1169, Dec. 1981
3. K. M. Ibrahim and S. N. Saloum, “An efficient residue to binary converter design,” IEEE Trans. Circuits Syst., vol. 35, no. 9, pp. 1156-1158, Sept. 1988.
4. A. Dhurkadas, “Comment on An efficient residue to binary converter design,” IEEE Trans. Circuits Syst., vol. 37, no. 6, pp. 849-850, June 1990.
5. A. P. Shenoy and R. Kumaresan, “Residue to binary converter for RNS arithmetic using only modular lookup tables,” IEEE Trans. Circuits Syst., vol. 35, no. 9, pp. 1158-1162, Sept. 1988.
6. T. R. N. Rao, Error Coding for Arithmetic Processors. New York: Academic, 1974.