Area-Time Efficient Modulo 2n - 1 Adder Design

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 41, Issue 7, 1994, Pages 463-467

  Efstathiou, C ^a   Nikolos, D ^b   Kalamatianos, J ^b  

^a Hellenic Telecommunications Organization SA (OTE)   (Greece)

^b UNIVERSITY OF PATRAS   (Greece)

Author keywords

Carry look ahead adders; end around carry adders; modulo 2n 1 adders; VLSI adders

Indexed keywords

ALGORITHMS; CARRY LOGIC; COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC DESIGN; LOGIC GATES; POLES AND ZEROS; VLSI CIRCUITS;

CARRY LOOK AHEAD ADDER; END AROUND CARRY ADDERS; VLSI ADDERS;

ADDERS;

EID: 0028463884     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.298378     Document Type: Article

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