A VLSI Algorithm for Direct and Reverse Conversion from Weighted Binary Number System to Residue Number System

IEEE Transactions on Circuits and Systems

Volumn 31, Issue 12, 1984, Pages 1033-1039

  Alia, Guiseppe ^a   Martinelli, Enrico ^a  

^a ISTI CNR   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; MATHEMATICAL TECHNIQUES - NUMBER THEORY;

DIRECT AND REVERSE; INTEGER NUMBERS; RESIDUE NUMBER SYSTEM (RNS); WEIGHTED BINARY NUMBER SYSTEM;

INTEGRATED CIRCUITS, VLSI;

EID: 0021691117     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCS.1984.1085465     Document Type: Article

References (11)

1. G. A. Jullien, “Residue number scaling and other operations using ROM arrays,” IEEE Trans. Comput., Vol. C-27, pp. 325–336, Apr. 1978.
2. W. K. Jenkins and B. J. Leon, “The use of residue number systems in the design of finite impulse response digital filters,” IEEE Trans. Circuits Syst., vol. CAS-24, pp. 191–201, Apr. 1977.
3. C. H. Huang, D. G. Peterson, H. E. Rauch, J. W. Teague, and D. F. Fraser, “Implementation of a fast digital processor using the residue number system,” IEEE Trans. Circuits Syst., vol. CAS-28, pp. 32–38, Jan. 1981.
4. M. A. Soderstrand, “A high-speed low cost recursive digital filter using residue number arithmetic,” Proc. IEEE, vol. 65, pp. 1065–1067, July 1977.
5. W. K. Jenkins, “Techniques for residue-to-analog conversion for residue-encoded digital filters,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 555–562, July 1978.
6. A. Baraniecka and G. A. Jullien, “On decoding techniques for residue number system realizations of digital signal processing hardware,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 935–936, Nov. 1978.
7. C. D. Thompson, “A Complexity Theory for VLSI,” Ph.D. dissertation, Carnegie-Mellon Univ., Computer Science Dep., Pittsburgh, PA, Aug. 1980.
8. R. P. Brent and H. T. Kung, “The area-time complexity of binary multiplication,” Tech. Rep. CMU-CS-79-136, July 1979.
9. C. Mead and L. Conway, Introduction to VLSI Systems. Reading, MA: Addison Wesley, 1980.
10. N. S. Szabo and R. J. Tanaka, Residue Arithmetic and its Application to Computer Technology. New York: McGraw-Hill, 1967.
11. R. P. Brent and H. T. Kung: “A regular layout for parallel adders,” IEEE Trans. Comput., vol. C-31, pp. 260–264, Mar. 1982.