Residue to Binary Conversion for RNS Arithmetic Using Only Modular Look-Up Tables

IEEE Transactions on Circuits and Systems

Volumn 35, Issue 9, 1988, Pages 1158-1162

  Shenoy, A P ^a   Kumaresan, R ^a  

^a UNIVERSITY OF RHODE ISLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SYSTEMS PROGRAMMING -- TABLE LOOKUP;

CHINESE REMAINDER THEOREM (CRT); RESIDUE NUMBER SYSTEM (RNS); RESIDUE TO BINARY CONVERSION;

COMPUTER METATHEORY;

EID: 0024070868     PISSN: 00984094     EISSN: None     Source Type: Journal    
DOI: 10.1109/31.7577     Document Type: Article

References (15)

1. N. S. Szabo and R. I. Tanaka, Residue Arithmetic and its Applications to Computer Technology. New York, McGraw-Hill, 1967.
2. W. K. Jenkins and B. J. Leon, “The use of residue number systems in the design of finite impulse response digital filters,” IEEE Trans. Circuits Syst., vol. CAS-24, pp. 191–201, Apr. 1977.
3. M. A. Soderstrand, “A high-speed low-cost recursive digital filtering using residue number arithmetic,” Proc. IEEE, vol. 65, pp. 1065–1067, July 1977.
4. W. K. Jenkins, “Techniques for residue-to-analog conversion for residue-Encoded Digital filters,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 555–562, July 1978.
5. A. Baraniecka and G. A. Jullien, “On decoding techniques for residue number system realizations of digital signal processing hardware,” IEEE Trans. Circuits Syst., vol. CAS-25, pp. 935–936, Nov. 1978.
6. A. Peled and B. Liu, “A new hardware realization of digital filters,” IEEE Trans. Acoust. Speech, Signal Processing, vol. ASSP-22, pp. 456–465, Dec. 1974.
7. M. A. Soderstrand, C. Vernia, and Jui-Hua Chang, “An improved residue number system digital-to-analog converter,” IEEE Trans. Circuits Syst., vol. CAS-30, pp. 903–906, Dec. 1983.
8. C. H. Huang, “A fully parallel mixed-radix conversion algorithm for residue number applications,” IEEE Trans. Comput., vol. C-32, pp. 398–402, Apr. 1983.
9. M. A. Bayoumi, G. A. Jullian, and W. C. Miller, “An efficient VLSI adder for DSP architectures based on RNS,” in IEEE Intl. Conf. on Acoustics, Speech, and Signal Processing, vol. 4 of 4, pp. 1457–1460, Mar. 1985.
10. N. S. Szabo and R. I. Tanaka, “Modes for VLSI implementation of residue number system arithmetic modulus,” in Proc. IEEE 6th Symp. on Comp. Arithmetic, pp. 174–182, June 1983.
11. A. P. Shenoy and R. Kumaresan, “A fast base extension method using redundant modulus in RNS,” IEEE Trans. Comput., to be published.
12. F. J. Taylor, “Residue arithmetic: A Tutorial with examples,” IEEE Computer Mag., pp. 50–62, May 1984.
13. C. H. Huang and F. J. Taylor, “A memory compression scheme for modular arithmetic,” IEEE Trans. Acoustics, Speech, Signal Processing, vol. ASSP-27, pp. 608–611, Dec. 1979.
14. M. A. Soderstrand, “A New Hardware Implementation of Modulo Adders for Residue Number Systems,” Proc. 26th Midwest Symp. on Circuits and Systems, Mexico, pp. 412–415, Aug. 1983.
15. A. P. Shenoy and R. Kumaresan, “A pipelined RNS to binary converter,” Proc. 29th Midwest Symp. Circuits and Systems, Lincoln, NE, Aug. 1986.