메뉴 건너뛰기




Volumn 29, Issue 10, 1994, Pages 1212-1219

A Simple Approach to Modeling CrossTalk in Integrated Circuits

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; EQUIVALENT CIRCUITS; LUMPED PARAMETER NETWORKS; MOS DEVICES; MOSFET DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MODELS; SPURIOUS SIGNAL NOISE; SUBSTRATES;

EID: 0028517306     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.315205     Document Type: Article
Times cited : (138)

References (6)
  • 1
    • 41549122718 scopus 로고
    • Comparison of SOI versus bulk silicon substrate crosstalk properties for mixed-mode ICs
    • I. Rahim, I. Lim, J. Foerstner, and B. Y. Hwang, “Comparison of SOI versus bulk silicon substrate crosstalk properties for mixed-mode IC’s,” in Proc. IEEE Int. SOI Conf., 1992, pp. 170–171.
    • (1992) Proc. IEEE Int. SOI Conf , pp. 170-171
    • Rahim, I.1    Lim, I.2    Foerstner, J.3    Hwang, B.Y.4
  • 2
    • 0027576336 scopus 로고
    • Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
    • April
    • D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid State Circuits, vol. 28, pp. 420–429, April 1993.
    • (1993) IEEE J. Solid State Circuits , vol.28 , pp. 420-429
    • Su, D.K.1    Loinaz, M.J.2    Masui, S.3    Wooley, B.A.4
  • 3
    • 0027668154 scopus 로고
    • Folded source-coupled coupled logic vs. CMOS static logic for low-noise mixed-signal ICs
    • Sept.
    • D. J. Allstot, S. Chee, S. Kiaei, and M. Shrivastawa, “Folded source-coupled coupled logic vs. CMOS static logic for low-noise mixed-signal IC’s,” IEEE Trans. Circuits and Syst. I, vol. 40, pp. 553–563, Sept. 1993.
    • (1993) IEEE Trans. Circuits and Syst. I , vol.40 , pp. 553-563
    • Allstot, D.J.1    Chee, S.2    Kiaei, S.3    Shrivastawa, M.4
  • 6
    • 0023983513 scopus 로고
    • Two and three-dimensional calculation of substrate resistance
    • March
    • L. Deferm, C. Claeys, and G. J. Declerk, “Two and three-dimensional calculation of substrate resistance,” IEEE Trans. Electron Devices, vol. 35, pp. 339–351, March 1988.
    • (1988) IEEE Trans. Electron Devices , vol.35 , pp. 339-351
    • Deferm, L.1    Claeys, C.2    Declerk, G.J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.