Analysis of Interconnection Delay on Very High-Speed LSI/VLSI Chips Using an MIS Microstrip Line Model

IEEE Transactions on Electron Devices

Volumn 31, Issue 12, 1984, Pages 1954-1960

  Hasegawa, Hideki ^a   Seki, Shouhei ^a  

^a HOKKAIDO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84889397436     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/T-ED.1984.21825     Document Type: Article

References (25)

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