-
1
-
-
0024886383
-
The guiding principle for BiCMOS scaling in ULSI's
-
S. Shukuri, A. Watanabe, R. Izawa, T. Nagano, and E. Takeda, “The guiding principle for BiCMOS scaling in ULSI's,” in 1989 Symp. on VLSI Technology Dig., p. 53.
-
(1989)
Symp. on VLSI Technology Dig.
, pp. 53
-
-
Shukuri, S.1
Watanabe, A.2
Izawa, R.3
Nagano, T.4
Takeda, E.5
-
3
-
-
0024908027
-
A BiCMOS channelless masterslice with on-chip voltage converter
-
H. Fukuda, S. Horiguchi, M. Urano, K. Fukami, K. Matsuda, N. Ohwada, and H. Akiya, “A BiCMOS channelless masterslice with on-chip voltage converter,” in ISSCCDig. Tech. Pap., 1989, p. 176.
-
(1989)
ISSCCDig. Tech. Pap.
, pp. 176
-
-
Fukuda, H.1
Horiguchi, S.2
Urano, M.3
Fukami, K.4
Matsuda, K.5
Ohwada, N.6
Akiya, H.7
-
4
-
-
0025531568
-
Fast-access BiCMOS SRAM architecture with a Vss generator
-
T. Douseki, Y. Ohmori, H. Yoshino, and J. Yamada, “Fast-access BiCMOS SRAM architecture with a Vss generator,” in 1990 Symp. on VLSI Circuits Dig., p. 45.
-
(1990)
Symp. on VLSI Circuits Dig.
, pp. 45
-
-
Douseki, T.1
Ohmori, Y.2
Yoshino, H.3
Yamada, J.4
-
5
-
-
84941604817
-
A BiCMOS analog master chip with versatile macro-cells
-
C. Tsuchiya, A. Ono, H. Tamada, T. Yamauchi, Y. Usui and U. Oshio, “A BiCMOS analog master chip with versatile macro-cells,” in Extended Abstracts 171st ECS Meet., 1987, vol. 87-1, p. 399.
-
(1987)
Extended Abstracts 171st ECS Meet.
, vol.87-1
, pp. 399
-
-
Tsuchiya, C.1
Ono, A.2
Tamada, H.3
Yamauchi, T.4
Usui, Y.5
Oshio, U.6
-
6
-
-
84941603356
-
High voltage BiCMOS process and its application
-
M. Shinohara, T. Kuroda, H. Kitaguchi, K. Tsubone, K. Matsumi, and K. Akahane, “High voltage BiCMOS process and its application,” in Extended Abstracts 171st ECS Meet., 1987, vol. 87-1, p. 417.
-
(1987)
Extended Abstracts 171st ECS Meet.
, vol.87-1
, pp. 417
-
-
Shinohara, M.1
Kuroda, T.2
Kitaguchi, H.3
Tsubone, K.4
Matsumi, K.5
Akahane, K.6
-
7
-
-
0024610567
-
Subquarter-micrometer gate-length p-channel and n-channel MOSFET's with extremely shallow source-drain junctions
-
M. Miyake, T. Kobayashi, and Y. Okazaki, “Subquarter-micrometer gate-length p-channel and n-channel MOSFET's with extremely shallow source-drain junctions,” IEEE Trans. Electron Devices, vol. 36, p. 392, 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, pp. 392
-
-
Miyake, M.1
Kobayashi, T.2
Okazaki, Y.3
-
8
-
-
0024888367
-
A high performance 0.22/um gate CMOS technology
-
Y. Okazaki, T. Kobayashi, M. Miyaka, T. Matsuda, K. Sakuma, Y. Kawai, and M. Takahashi, “A high performance 0.22/um gate CMOS technology,” in 1989 Symp. on VLSI Technology Dig., p. 13.
-
(1989)
Symp. on VLSI Technology Dig.
, pp. 13
-
-
Okazaki, Y.1
Kobayashi, T.2
Miyaka, M.3
Matsuda, T.4
Sakuma, K.5
Kawai, Y.6
Takahashi, M.7
-
9
-
-
0025416309
-
High performance subquarter-micrometer gate CMOS technology
-
Y. Okazaki, T. Kobayashi, M. Miyake, T. Matsuda, K. Sakuma, Y. Kawai, M. Takahashi, and K. Kanisawa, “High performance subquarter-micrometer gate CMOS technology,” IEEE Electron Device Lett., vol. 11, p. 134, 1990.
-
(1990)
IEEE Electron Device Lett.
, vol.11
, pp. 134
-
-
Okazaki, Y.1
Kobayashi, T.2
Miyake, M.3
Matsuda, T.4
Sakuma, K.5
Kawai, Y.6
Takahashi, M.7
Kanisawa, K.8
-
10
-
-
0024608379
-
Feasibility of high-energy boron implantation for p-type retrograde well formation
-
K. Ohyu, T. Suzuki, T. Yamanaka, and N. Natsuaki, “Feasibility of high-energy boron implantation for p-type retrograde well formation,” Nucl. Instrum. andMeth., vol. B37/38, p. 749, 1989.
-
(1989)
Nucl. Instrum. andMeth.
, vol.B37/38
, pp. 749
-
-
Ohyu, K.1
Suzuki, T.2
Yamanaka, T.3
Natsuaki, N.4
-
11
-
-
0022682298
-
MeV-energy B +, P+ and As+ ion implantation into Si
-
M. Tamura, N. Natsuaki, Y. Wada, and E. Mitani, “MeV-energy B +, P+ and As+ ion implantation into Si,” Nucl. Instrum. andMeth., vol. B21, p. 438, 1987.
-
(1987)
Nucl. Instrum. andMeth.
, vol.21 B
, pp. 438
-
-
Tamura, M.1
Natsuaki, N.2
Wada, Y.3
Mitani, E.4
-
12
-
-
0020828727
-
MeV-energy As+ implantation into Si: Extended-defect reduction and planar n-p-n transistor fabrication
-
M. Takahashi, S. Konaka, and K. Kajiyama, “MeV-energy As+ implantation into Si: Extended-defect reduction and planar n-p-n transistor fabrication,” J. Appl. Phys., vol. 54, p. 6041, 1983.
-
(1983)
J. Appl. Phys.
, vol.54
, pp. 6041
-
-
Takahashi, M.1
Konaka, S.2
Kajiyama, K.3
-
13
-
-
0025545335
-
Low temperature ion implantation for buried layer formation
-
T. Suzuki, H. Yamaguchi, S. Ohno, and N. Natsuki, “Low temperature ion implantation for buried layer formation,” in Extended Abstracts 22nd (1990 Int.) Conf. on Solid State Devices and Materials, p. 1163.
-
Extended Abstracts 22nd (1990 Int.) Conf. on Solid State Devices and Materials
, pp. 1163
-
-
Suzuki, T.1
Yamaguchi, H.2
Ohno, S.3
Natsuki, N.4
-
14
-
-
0015770573
-
latchup in CMOS integrated circuits
-
B. L. Gregory and B. D. Shafer, “latchup in CMOS integrated circuits,” IEEE Trans. Nucl. Sci., vol. NS-20, p. 293, 1973.
-
(1973)
IEEE Trans. Nucl. Sci.
, vol.NS-20
, pp. 293
-
-
Gregory, B.L.1
Shafer, B.D.2
-
15
-
-
0021204461
-
A better understanding of CMOS latchup
-
G. J. Hu, “A better understanding of CMOS latchup,” IEEE Trans. Electron Devices, vol. ED-31, p. 62, 1984.
-
(1984)
IEEE Trans. Electron Devices
, vol.ED-31
, pp. 62
-
-
Hu, G.J.1
-
16
-
-
0017973440
-
Si-controlled avalanche logic
-
W. Tantraporn, S. P. Yu, and W. R. Cady, “Si-controlled avalanche logic,” IEEE Trans. Electron Devices, vol. ED-25, p. 520, 1978.
-
(1978)
IEEE Trans. Electron Devices
, vol.ED-25
, pp. 520
-
-
Tantraporn, W.1
Yu, S.P.2
Cady, W.R.3
-
17
-
-
0024172243
-
A new static memory cell based on reverse base current (RBC) effect of bipolar transistor
-
K. Sakui, T. Hasegawa, T. Fuse, S. Watanabe, K. Ohuchi, and F. Masuoka, “A new static memory cell based on reverse base current (RBC) effect of bipolar transistor,” in IEDM Tech. Dig., 1989, p. 44.
-
(1989)
IEDM Tech. Dig.
, pp. 44
-
-
Sakui, K.1
Hasegawa, T.2
Fuse, T.3
Watanabe, S.4
Ohuchi, K.5
Masuoka, F.6
-
18
-
-
0025495106
-
3.2 GHz, 0.2 03BC m Gate CMOS 1/8 dynamic frequency divider
-
Y. Kado, Y. Okazaki, M. Suzuki, and T. Kobayashi, “3.2 GHz, 0.2 03BC m Gate CMOS 1/8 dynamic frequency divider,” Electron. Lett., vol. 26, p. 1684, 1990.
-
(1990)
Electron. Lett.
, vol.26
, pp. 1684
-
-
Kado, Y.1
Okazaki, Y.2
Suzuki, M.3
Kobayashi, T.4
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