The effect of the elevated source/drain doping profile on performance and reliability of deep submicron mosfet's

IEEE Transactions on Electron Devices

Volumn 44, Issue 9, 1997, Pages 1491-1498

  Sun, Jie J ^a,b,c   Bartholomew, Robert F ^a,b   Bellur, Kashyap ^a,b,c   Srivastava, Anadi ^a,b,c   Osburn, Carlton M ^a,b   Masnari, Nino A ^a,b  

^a North Carolina State University   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c Microelectronics Research Laboratory   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING;

DRAIN INDUCED BARRIER LOWERING (DIBL); SOURCE/DRAIN (SD) JUNCTIONS;

MOSFET DEVICES;

EID: 0031236219     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.622606     Document Type: Article

References (19)

1. G.G. Shahidi, J. Warnock, S. Fischer, P. A. MacFarland, A. Acovic, S. Subbanna, E. Ganin, E. Crabbe, J. Comfort, J. Y.-C. Sun, T. H. Ning, and B. Davari, "High-performance devices for a 0.15-μm CMOS technology," IEEE Electron Device Lett., vol. 12, p. 466, 1993.
2. M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, T. Ohguro, and H. Iwai, "Sub-50-nm gate length N-MOSFET with 10 nm phosphorous source and drain junctions," in IEDM Tech. Dig., 1993, p. 119.
3. S. Wong, D. Bradbury, D. Chen, and K. Chiu, "Elevated source/drain MOSFET," in IEDM Tech. Dig., 1984, p. 634.
4. + n junction utilizing selective silicon growth and rapid thermal annealing," in IEDM Tech. Dig., 1987, p. 590.
5. J.R. Pfiester, R. D. Sivan, H. M. Liaw, C. A. Seelbach, and C. D. Gunderson, "A self-aligned elevated source/drain MOSFET," IEEE Electron Device Lett., vol. 11, p. 365, 1990.
6. J.E. Chung, M. C. Jeng, J. E. Moon, P. K. Ko, and C. Hu, "Low-voltage hot-electron current and degradation in deep-submicron MOSFET's," IEEE Trans. Electron Devices, vol. 37, p. 1651, 1990.
7. T. Mizuno, A. Toriumi, M. Iwase, M. Takahashi, H. Niiyama, M. Fukumoto, and M. Yoshimi, "Hot-carrier effects in 0.1-μm gate length CMOS devices," in IEDM Tech. Dig., 1992, p. 695.
8. H. Shin, A.F. Tasch, T. J. Bordelon, and C. M. Maziar, "MOSFET drain engineering analysis for deep-submicrometer dimensions: A new structural approach," IEEE Trans. Electron Devices, vol. 39, p. 1922, 1992.
9. H. Tian, K.W. Kim, J. R. Hauser, N. A. Masnari, and M. A. Littlejohn, "Effects of profile-doped elevated source//drain structures on deep-submicron MOSFET's," Solid-State Electron., vol. 38, p. 573, 1995.
10. Y.-K. Wu, "Fabrication and characterization of the hot-carrier suppressed (HCS) MOSFET," Ph.D. dissertation, Univ. Texas, Austin, 1995.
11. K.X. Zhang, C. M. Osburn, G. Hames, C. Parker, and A. Bayoumi, "A 0.25-μm MOSFET technology using in situ rapid thermal gate dielectrics," J. Electrochem. Soc., vol. 143, p. 744, 1996.
12. J. Sun, R.F. Bartholomew, K. Bellur, A. Srivastava, C. M. Osburn, R. Westhoff, and B. Fowler, J. Electrochem. Soc., submitted for publication.
13. C. Mazure, J. Fitch, and C. Gunderson, "Facet engineered elevated source/drain by selective Si epitaxy for 0.35 micron MOSFET's," in IEDM Tech. Dig., 1992, p. 853.
14. D.A. Antoniadis and J. E. Chung, "Physics and technology of ultra-short-channel MOSFET devices," in IEDM Tech. Dig., 1991, p. 21.
15. F. Assaderaghi, P.K. Ko, and C. Hu, "Observation of velocity overshoot in silicon inversion layers," IEEE Electron Device Lett., vol. 14, p. 484, 1993.
16. J.Y. Tsai, J. Sun, K. F. Yee, and C. M. Osburn, "DIBL considerations of extended drain structure for 0.1-μm MOSFET's," IEEE Electron Device Lett., vol. 17, p. 331, 1996.
17. Y. Nakahara, K. Takeuchi, T. Tatsumi, Y. Ochiai, S. Manako, S. Samukawa, and A. Furukawa, "Ultrashallow in situ-doped raised source/drain structure for sub-tenth-micron CMOS," in VLSI Symp. Tech. Dig., 1996, p. 174.
18. S. Thompson, P. Packan, and M. Bohr, "Linear versus saturated drive current: Tradeoffs in super steep retrograde well engineering," in VLSI Symp. Tech. Dig., 1996, p. 154.
19. F.-C. Hsu and H.R. Grinolds, "Structure-enhanced MOSFET degradation due to hot-electron injection," IEEE Electron Device Lett., vol. EDL-5, p. 71, 1984.