High-Performance Devices for a 0.15-μm CMOS Technology

IEEE Electron Device Letters

Volumn 14, Issue 10, 1993, Pages 466-468

  Shahidi, G G ^a   Warnock, James ^a   Fischer, S ^a   McFarland, P A ^a   Acovic, Alexandre ^a   Subhanna, S ^a   Ganin, E ^a   Crabbé, Emmanuel ^a   Comfort, James ^a   Sun, Jack Y C ^a   Ning, Tak H ^a   Davari, Bijan ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMORPHOUS MATERIALS; ARSENIC; BORON COMPOUNDS; GATES (TRANSISTOR); INTEGRATED CIRCUIT MANUFACTURE; ION IMPLANTATION; PERFORMANCE; SEMICONDUCTING ANTIMONY; SEMICONDUCTING INDIUM; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS; ULSI CIRCUITS;

CHANNEL IMPLANTS; PREAMORPHIZATION; SHORT CHANNEL EFFECTS;

CMOS INTEGRATED CIRCUITS;

EID: 0027680704     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.244732     Document Type: Article

References (7)

1. B. Davari et al., “A high performance 0.25 μm CMOS technology,” in IEDM Tech. Dig., 1988, p. 56.
2. G. A. Sai-Halazs et al., “Experimental technology and characterization of self-aligned 0.1 μm-gate-length low temperature operation nMOS devices,” in IEDM Tech. Dig., 1987, p. 397.
3. A. Toriumi et al., “A high speed 0.1 μm CMOS devices operating at room temperature,” in Ext. Abstr. Int. Conf. Solid State Devices and Mater., 1992, p. 487.
4. G. Shahidi et al., “Indium channel implant for improved short channel behavior of sub-micron NMOSFET’s,” IEEE Electron Device Lett., vol. 14, pp. 409–411, Aug. 1993.
5. B. Davari, E. Ganin, D. Harame, and G. A. Sai-Halsaz, “A new preamorphization technique for very shallow P+-N junctions,” in Symp. VLSI Tech. Dig., 1989, p. 27.
6. Y. Taur et al., “High performance 0.1 μm pMOSFET,” in IEDM Tech. Dig., 1992, p. 901.
7. G. Shahidi et al., “A high performance 0.15 μm CMOS,” in Tech. Dig. Symp. VLSI Tech., 1993, p. 93.