Routing for array-type FPGA's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 16, Issue 5, 1997, Pages 506-518

  Wu, Yu Liang ^a   Marek Sadowska, Malgorzata ^b  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b University of California   (United States)

Author keywords

Fpga routing; Greedy coupling optimization scheme

Indexed keywords

COMPUTER ARCHITECTURE; HEURISTIC METHODS; LOGIC GATES; OPTIMIZATION; PARALLEL ALGORITHMS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); GREEDY COUPLING OPTIMIZATION SCHEME;

PARALLEL PROCESSING SYSTEMS;

EID: 0031144824     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.631213     Document Type: Article

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