Efficient router for 2-D field programmable gate arrays

Proceedings of the European Design and Test Conference

Volumn , Issue , 1994, Pages 412-416

  Wu, Yu Liang ^a   Marek Sadowska, Malgorzata ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ARRAYS; COMMUNICATION CHANNELS (INFORMATION THEORY); CRITICAL PATH ANALYSIS; ELECTRIC NETWORK ANALYSIS; HEURISTIC PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; SEMICONDUCTOR DEVICE MODELS;

BIN-PACKING HEURISTIC BASED GREEDY ROUTER; FIELD PROGRAMMABLE GATE ARRAYS; ROUTING LENGTH;

COMPUTER ARCHITECTURE;

EID: 0027940885     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)