Layout driven logic synthesis for FPGAs

Proceedings - Design Automation Conference

Volumn , Issue , 1994, Pages 308-313

  Chang, Shih Chieh ^a   Cheng, Kwang Ting ^a   Woo, Nam Sung ^a   Marek Sadowska, Malgorzata ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRING; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL TRANSFORMATIONS; REDUNDANCY; TABLE LOOKUP;

ALTERNATIVE WIRES; FIELD PROGRAMMABLE GATE ARRAY; LOGIC DRIVEN LOGIC SYNTHESIS;

COMPUTER AIDED LOGIC DESIGN;

EID: 0028599640     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/196244.196388     Document Type: Conference Paper

References (9)