Effective buffer insertion of clock tree for high-speed VLSI circuits

Microelectronics Journal

Volumn 23, Issue 4, 1992, Pages 291-300

  Wu, Bo ^a   Sherwani, Naveed A ^a  

^a WESTERN MICHIGAN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC CIRCUITS, TIMING - APPLICATIONS; INTEGRATED CIRCUITS, VLSI - DESIGN; INTEGRATED CIRCUITS, VLSI - MATHEMATICAL MODELS; MATHEMATICAL TECHNIQUES - ALGORITHMS;

CLOCK DELAY; CLOCK SKEW;

INTEGRATED CIRCUITS, VLSI;

EID: 0026899868     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2692(92)90026-W     Document Type: Article

References (11)

1. Reduction of clock delays in VLSI structures
2. Design and analysis of a hierarchical clock distribution system for synchronous standard cell/macrocell VLSI
3. Clock routing for high-performance ICs
4. High-performance clock routing based on recursive geometric matching
5. Clock layout for high-performance ASIC based on weighted center algorithm
6. Asynchronous and clocked control structures for VLSI based interconnection networks
7. Buffer placement in distributed RC-tree networks for minimal Elmore delay
8. Optimal interconnection circuits for VLSI
9. Optimum buffer circuits for driving long uniform lines
10. Signal delay in general RC networks