Analytic Transient Solution of General MOS Circuit Primitives

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 11, Issue 6, 1992, Pages 719-731

  Shih, Yung Ho ^a   Kang, Sung Mo ^b  

^a MICROSOFT   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUITS, DIGITAL - TRANSIENTS; MATHEMATICAL TECHNIQUES - DIFFERENTIAL EQUATIONS; SEMICONDUCTOR DEVICES, MOS;

FAST TIMING SIMULATIONS; MOS CIRCUIT PRIMITIVES; MOS I-V CHARACTERISTICS; SWITCH-LEVEL SIMULATIONS;

INTEGRATED CIRCUITS, DIGITAL;

EID: 0026881092     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.137517     Document Type: Article

References (29)

1. V. B. Rao, T. N. Trick, and I. N. Hajj, “A table-driven delay-operator approach to timing simulation of MOS VLSI circuits,” in Proc. IEEE Int. Conf. Computer Design (New York), Nov. 1983, pp. 445–448.
2. V. B. Rao, “Switch-level timing simulation of MOS VLSI circuits,” Ph.D. thesis, Department of Electrical and Computer Engineering, University of Illinois, Urbana, 1985.
3. F.-P. Lai, V. B. Rao, and T. N. Trick, “JADE: A hierarchical switch level timing simulator,” in Proc. IEEE Int. Symp. Circuits Syst. (Philadelphia), May 1987, pp. 592–595.
4. H. N. Nham and A. K. Bose, “A multiple delay simulator for MOS LSI circuits,” in Proc. 17th Design Automat. Conf., June 1980, pp. 610–617.
5. T. Tokuda, K. Okazaki, K. Sakashita, I. Ohkura, and T. Enomoto, “Delay-time modeling for ED MOS logic LSI,” IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 129–134, July 1983.
6. Y. H. Jun and S. B. Park, “An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 1027–1032, Sept. 1989.
7. D. Overhauser, I. N. Hajj, and V. B. Rao, “Switch-level timing analysis of VLSI MOS circuits including parasitics,” in Proc. IEEE Int. Symp. Circuits Syst. (San Jose, CA), May 1986, pp. 761–764.
8. D. Overhauser and I. N. Hajj, “A tabular macromodeling approach to fast timing simulation including parasitics,” in Proc. IEEE Int. Conf. Computer-Aided Design (Santa Clara, CA), Nov. 1988.
9. Carl E. Pearson, Handbook of Applied Mathematics. New York: Van Nostrand Reinhold, 1974, ch. 6.
10. L. J. Slater, Confluent Hypergeometric Functions. Cambridge: Cambridge University Press, 1960.
11. H. Buchholz, The Confluent Hypergeometric Function. New York: Springer-Verlag, 1969, ch. 1.
12. G. N. Watson, A Treatise on the Theory of Bessel Functions. New York: Macmillan, 1945, pp. 92–94.
13. M. Shoji, CMOS Digital Circuit Technology. Englewood Cliffs, NJ: Prentice-Hall, 1987, ch. 3.
14. J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits. Reading, MA: Addison-Wesley, 1988, ch. 4.
15. S. R. Vemuru and A. R. Thorbjomsen, “A CMOS inverter model for the propagation delay evaluation,” in Proc. 32nd Midwest Symp. Circuits and Systems (Urbana, IL), Aug. 1989, pp. 563–566.
16. S. R. Vemuru and A. R. Thorbjomsen, “A model for delay evaluation of a CMOS inverter,” in Proc. IEEE Int. Symp. Circuits Syst., (New Orleans), May 1990, pp. 89–92.
17. H. Shichman and D. A. Hodges, “Modeling and simulation of insulated gate field effect transistor switching circuits,” IEEE J. Solid-State Circuits, vol. SC-3, pp. 245–259, Sept. 1968.
18. A. Vladimirescu and S. Liu, “The simulation of MOS integrated circuits using SPICE 2,” Memorandum UCB/ERL M80/7, University of California, Berkeley, Feb. 1980.
19. G. Merckel, J. Borel, and N. Z. Cupcea, “An accurate large-signal MOS transistor model for use in computer-aided design,” IEEE Trans. Electron Devices, vol. ED-19, pp. 681–690, May 1972.
20. U. J. Knottnerus, Approximation Formulae for Generalized Hypergeometric Functions for Large Values of the Parameters. Groningen: J. B. Wolters, 1960.
21. H. Exton, Multiple Hypergeometric Functions and Applications. Chichester: Ellis Horwood, 1976, ch. 1.
22. H. Skovgaard, Uniform Asymptotic Expansions of Confluent Hyper-geometric Functions and Whittaker Functions. Copenhagen: Jul. Gjellerups Forlag, 1966.
23. National Bureau of Standards, U.S. Department of Commerce. Tables of the Confluent Hypergeometric Functions (n/2, 1/2; x). Washington, DC: United States Government Printing Office, 1949.
24. E. Kreyszig, Advanced Engineering Mathematics. New York: Wiley, 1972, ch. 3.
25. M. Tenenbaum and H. Pollard, Ordinary Differential Equations. New York: Harper & Row, 1963. ch.4, chs. 9 and 11.
26. T. J. I'A. Bromwich, An Introduction to the Theory of Infinite Series. London: Macmillan, 1947. ch. 7, pp. 324–354.
27. K. Knopp, Theory and Application of Infinite Series. London: Blackie & Son, 1951, ch. 14.
28. Y.-H. Shih and S. M. Kang, “ILLIADS: A new fast MOS timing simulator using direct-equation solving approach,” in Proc. ACM/ IEEE Design Auto. Conf., June 1991.
29. D. A. Hodges and H. G. Jackson, Analysis and Design of Digital Integrated Circuits. New York: McGraw-Hill, 1983.