Performance of Synchronous and Asynchronous Schemes for VLSI Systems

IEEE Transactions on Computers

Volumn 41, Issue 7, 1992, Pages 858-872

  Afghahi, Morteza ^a   Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Arbiter; asynchronous; clocking delay model; digital; metastability; scaling; synchronization; synchronous; VLSI

Indexed keywords

COMPUTER SYSTEMS, DIGITAL--SYNCHRONIZATION;

ASYNCHRONOUS SYSTEMS;

INTEGRATED CIRCUITS, VLSI;

EID: 0026890711     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.256454     Document Type: Article

References (50)

1. C. Mead and L. Conway, Introduction to VLSI systems. Reading, MA: Addison-Wesley, 1980.
2. D. F. Wann and M. A. Franklin, “Asynchronous and clocked control structures of VLSI-based interconnection networks,” IEEE Trans. Comput. vol. C-32, pp. 284–293, Mar. 1983.
3. S. Y. Kung and R. J. Gal-Ezar, “Synchronous versus asynchronous computation in VLSI array processors,” SPIE, vol. 341, pp. 53–65, 1982.
4. A. L. Fisher and H. T. Kung, “Synchronizing large VLSI processor arrays,” IEEE Trans. Comput., vol. C-34, pp. 734–740, Aug. 1985.
5. E. Arjomandi, M. J. Fisher, and N. A. Lynch, “Efficiency of synchronous versus asynchronous distributed systems,” J. ACM, vol. 30, pp. 449–456, July 1983.
6. D. Zhou, F. P. Preparata, and S. M. Kang, “Interconnection delay in very high-speed VLSI,” IEEE Trans. Circuit Syst., vol. 38, no. 7, pp. 779–790, July 1991.
7. J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE J. Solid-State Circuits, vol. 24, no. 1, 62–70, Feb. 1989.
8. F. Anceau, “A synchronous approach for clocking VLSI systems,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 51–56, Feb. 1982.
9. M. Afghahi and C. Svensson, “A unified single phase clocking scheme for VLSI systems,” IEEE J. Solid-State Circuits, vol. 25, no. 1, pp. 225–233, Feb. 1990.
10. C. F. Molnar, T. Fang, and F. U. Rosenberger, “Synthesis of delay-insensitive modules,” in Proc. Chapel-Hill Conf. VLSI, 1985, 67–86.
11. F. U. Rosenberger, C. E. Molnar, T. J. Chaney, and T. Fanf, “Q-modules: Internally clocked delay-insensitive modules,” IEEE Trans. Comput., vol. 37, no. 9, pp. 1005–1018, Sept. 1988.
12. M. Pchoucek, “Anomalous response time of input synchronizers,” IEEE Trans. Comput. vol. C-25, 133–139, 1975.
13. W. Y. Lim and J. R. Cox, “Clocks and the performance of synchronizers,” Proc. IEE, vol. 130, pt. E, pp. 57–64, Mar. 1983.
14. W. Lim, “Design methodology for stopable clock systems,” Proc. IEE, vol. 133 pt.E. pp. 65–69, Jan. 1986.
15. S. H. Unger and C. Tan, “Clocking schemes for high-speed digital systems,” IEEE Trans. Comput., vol. C-35, 880–895, 1986.
16. E. B. Friedman and S. Powel, “Design and analysis of a hierarchial clock distribution system for synchronous standard cell/macrocell VLSI,” IEEE J. Solid-State Circuits, vol. SC-21, pp.240–246, Apr.1986.
17. M. Hatamian and G.L. Cash, “Parallel bit-level VLSI designs for high-speed signal processing,” Proc. IEEE, vol. 75, no. 9, pp. 1192–1202, Sept. 1987.
18. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI. Reading, MA: Addison-Wesley, 1990.
19. H. B. Bakoglu and J. D. Meindl, “Optimal interconnection circuit for VLSI,” IEEE Trans. Electron Devices, vol. ED-32, pp. 903–909, May 1985.
20. J. O. Tuazon, J. C. Peterson, M. Pniel, and D. Liberman, “CalTech/JPL Mark II Hypercube concurrent processor,” in Proc. 1985 Int. Conf. Parallel Processing, Aug. 1985, 666–673.
21. F. Rosenberger and T. J. Chaney, “Flip-flop resolving time test circuit,” IEEE J. Solid-State Circuits, vol. SC-17, pp. 731–738, Aug. 1982.
22. A. Papoulis, Probability, Random Variables and Stochastic Process. Tokyo: McGraw-Hill, Kogakusha, 1965.
23. K. R. Lakshmikumar, A. Hadaway, and M. A. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE J. Solid-State Circuits, vol. SC-21, pp. 1057–1066, Dec. 1986.
24. Y. El-Mansy, “MOS device and technology constraints in VLSI,” IEEE J. Solid-State Circuits, vol. SC-17, no. 2, 197–203, Apr. 1982.
25. M. Hurtado, “Structure and performance of asymptotically bistable dynamical systems,” D.Sc. dissertation, Dep. EE. Washington Univ., St., Louis, MO, 1975.
26. M. Afghahi and C. Svensson, “Calculation of clock path delay and skew in VLSI synchronous systems,” in Proc. IEEE Euro. Conf. Circuit Theory and Design, Brighton, England, Sept. 1989, pp. 256–269.
27. INMOS, IMST424 Transputer Reference Manual, Nov. 1984.
28. M. J. Stucki and J. K. Cox, “Synchronization strategies,” in Proc. Caltech Conf. VLSI, Jan. 1979, 375–393.
29. H. Masuda, M. Nakai, and M. Kubo, “Characteristics and limitation of scaled-down MOSFET’s due to two-dimentional field effect,” IEEE Trans. Electron Devices, vol. ED-26, pp. 980–986, June 1979.
30. T. Kacprzak and A. Albicki, “Analysis of metastable operation in RS CMOS flip-flops,” IEEE J. Solid-State Circuits, vol. SC-22, pp. 57–64, Feb. 1987.
31. T. J. Chaney and F. U. Rosenberger, “Characterizarion and scaling of MOS flip-flop performance in synchronizer applications,” in Proc. Caltech Conf. VLSI, Jan. 1979, pp. 357–374.
32. B. Randell, P. A. Lee, and P. C. Treleaven, “Reliability issues in computing design,” ACM Comput. Surveys, no. 10, pp. 123–165, 1987.
33. M. Afghahi and C. Svensson, “A scalable synchronous system,” in Proc. IEEE Symp. Circuits Syst., Finland, 1988, pp. 471–474.
34. H. Weste and K. Eshraghian, Principles of CMOS VLSI Design-A System Perspective. Reading, MA: Addison-Wesley 1985.
35. C. Svensson, “VLSI physics,” Integration, vol. 1, pp. 3–19, 1983.
36. C. Svensson, “Signal resynchronization in VLSI systems,” Integration, vol. 4, pp. 75-80, 1986.
37. Chapiro, Ph.D dissertation, STANCS-84-1026, Dep. Comput. Sci., Stanford Univ., Stanford CA 94305, Oct. 1984.
38. H. Cong, J. M. Anderews, D. M. Boulin, S. Fang, S. J. Hillenius, and J. A. Michejda, “Multigigahertz CMOS dual-modules prescalar IC,” IEEE J. Solid-State Circuits, vol. 23, no. 5, pp. 1189–1194, Oct. 1988.
39. L. Kleeman and A. Cantoni, “Metastable behavior in digital systems,” IEEE Design Test Comput. pp. 4–19, Dec. 1987.
40. D. M. Brown, M. Ghezzo, and J. M. Pimbley, “Trends in advanced process technology-Submicron CMOS device design and process requirements,” Proc. IEEE, vol. 74, no. 12, pp. 1678–1702, Dec. 1986.
41. W. A. Holton and R. K. Cavin, III, “A perspective on CMOS technology trends,” Proc. IEEE, vol. 74, no. 12, 1646–1668, Dec. 1986.
42. C. E. Leiserson and J. B. Saxe, “Optimizing synchronous systems,” in Proc. IEEE Symp. Foundations Comput. Sci., 1981, pp. 23–36.
43. S. D. Kugelmass and K. Steiglitz, “A probabilistic model for clock skew,” in Proc. Int. Conf. Systolic Arrays, San Diego, CA, 1988, pp. 545–554.
44. K. R. Lakshmi Kumar, “Characterization and modeling of mismatch in MOS devices and application to precision analog design,” Ph.D. dissertation, Carlton Univ., Ottawa, Ont., Canada, 1985.
45. H. Cramer, Mathematical Methods of Statistics. Princeton, NJ: Princeton Univ. Press, 1946.
46. E. G. Friedman, “Performance limitations in synchronous digital systems,” Ph.D. dissertation, Univ. California, Irvine, CA, 1989.
47. C. Seitz, “Concurrent VLSI architectures,” IEEE Trans. Comput., vol. C-33, no. 12, pp. 1247–1265, Dec. 1984.
48. S. M. Kang, “Metal-metal matrix (M3) for high-speed MOS VLSI layout,” IEEE Trans. Comput.-Aided Design, vol. CAD-6, no. 6, pp.886–891, Sept. 1987.
49. J. P. Fishburn, “Clock skew optimization,” IEEE Trans. Comput., vol. 39, no. 7, pp. 945–951, July 1990.
50. M. Afghahi, “A 512, 16-b bit-serial sorter chip,” IEEE J. Solid-State Circuits, vol. 26, pp. 1452-1457, Oct. 1991.