Clock distribution design in VLSI circuits. An overview

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1993, Pages 1475-1478

  Friedman, Eby G ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DATA COMMUNICATION SYSTEMS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; TIMING CIRCUITS;

CLOCK DISTRIBUTION NETWORKS; DATA SIGNALS; GATE ARRAYS;

VLSI CIRCUITS;

EID: 0027289923     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (53)