Modeling of the parasitic transistor-induced drain breakdown in MOSFET's

IEEE Transactions on Electron Devices

Volumn 43, Issue 12, 1996, Pages 2190-2196

  Wong, Hei ^a  

^a CITY UNIVERSITY OF HONG KONG   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; CALCULATIONS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC FIELD EFFECTS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; SUBSTRATES; THERMAL EFFECTS; VOLTAGE MEASUREMENT;

BIASING; CHANNEL LENGTH; MINIMOS SIMULATION; PARASITIC TRANSISTOR DRAIN BREAKDOWN; SUBSTRATE RESISTANCE; VOLTAGE DROP;

ELECTRIC BREAKDOWN;

EID: 0030410867     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.544391     Document Type: Article

References (14)

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