Incorporating performance and testability constraints during binding in high-level synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 10, 1996, Pages 1212-1225

  Mujumdar, Ashutosh ^a,c   Jain, Rajiv ^a   Saluja, Kewal ^b  

^a Alta Group   (United States)

^b HEWLETT PACKARD COMPANY   (United States)

^c University of Wisconsin Madison   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTRIC WIRING; HEURISTIC METHODS; HIGH LEVEL LANGUAGES; MATHEMATICAL MODELS; PERFORMANCE; PROBLEM SOLVING; SHIFT REGISTERS;

BINDING; HIGH LEVEL SYNTHESIS; POINT TO POINT INTERCONNECTION; REGISTER TRANSFER LEVEL; TESTABILITY;

COMPUTER AIDED LOGIC DESIGN;

EID: 0030264868     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.541441     Document Type: Article

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