-
1
-
-
84941468802
-
A global optimization approach to architectural synthesis of VLSI digital synchronous systems with analog and asynchronous interfaces
-
Dept. Elec. Comput. Eng., Univ. of Waterloo, Waterloo, Ont., Canada, July
-
C. H. Gebotys, “A global optimization approach to architectural synthesis of VLSI digital synchronous systems with analog and asynchronous interfaces,” Ph.D. dissertation, Dept. Elec. Comput. Eng., Univ. of Waterloo, Waterloo, Ont., Canada, July 1991.
-
(1991)
Ph.D. dissertation
-
-
Gebotys, C.H.1
-
3
-
-
0024942755
-
A new integer linear programming formulation for the scheduling problem in data path synthesis
-
J. Lee, Y. Hsu, and Y. Lin, “A new integer linear programming formulation for the scheduling problem in data path synthesis,” in Proc. Int. Conf. Computer-Aided Design, 1989, pp. 20–23.
-
(1989)
Proc. Int. Conf. Computer-Aided Design
, pp. 20-23
-
-
Lee, J.1
Hsu, Y.2
Lin, Y.3
-
4
-
-
0020544208
-
A formal method for the specification, analysis and design of register-transfer-level digital logic
-
Jan
-
L. Hafer and A. Parker, “A formal method for the specification, analysis and design of register-transfer-level digital logic,” IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 4–17, Jan. 1983.
-
(1983)
IEEE Trans. Computer-Aided Design
, vol.CAD-2
, pp. 4-17
-
-
Hafer, L.1
Parker, A.2
-
5
-
-
0026139605
-
A formal approach to the scheduling problem in high-level synthesis
-
C-T. Hwang, J-H. Lee, and Y-C. Hsu, “A formal approach to the scheduling problem in high-level synthesis,” IEEE Trans, on Computer-Aided Design, vol. 10, pp. 464–475, 1991.
-
(1991)
IEEE Trans. on Computer-Aided Design
, vol.10
, pp. 464-475
-
-
Hwang, C.-T.1
Lee, J.-H.2
Hsu, Y.-C.3
-
6
-
-
0024706222
-
Algorithms for hardware allocation in data path synthesis
-
July
-
S. Devadas and A. R. Newton, “Algorithms for hardware allocation in data path synthesis,” IEEE Trans. Computer-Aided Design, vol. 8, pp. 768–781, July 1989.
-
(1989)
IEEE Trans. Computer-Aided Design
, vol.8
, pp. 768-781
-
-
Devadas, S.1
Newton, A.R.2
-
9
-
-
84941440989
-
A global optimization approach for architectural synthesis
-
Waterloo Ont., Canada, UW/ICR 91–01
-
C. H. Gebotys and M. I. Elmasry, “A global optimization approach for architectural synthesis,” Univ. of Waterloo, Waterloo Ont., Canada, UW/ICR 91–01, 1991.
-
(1991)
Univ. of Waterloo
-
-
Gebotys, C.H.1
Elmasry, M.I.2
-
10
-
-
0020815626
-
Solving large scale zero-one linear programming problems
-
Sept
-
H. Crowder, E. L. Johnson, and M. Padberg, “Solving large scale zero-one linear programming problems,” Operations Res., vol. 31, no. 5, pp. 803–834, Sept. 1983.
-
(1983)
Operations Res.
, vol.31
, Issue.5
, pp. 803-834
-
-
Crowder, H.1
Johnson, E.L.2
Padberg, M.3
-
13
-
-
0026174907
-
Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis
-
C. H. Gebotys and M. I. Elmasry, “Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis,” in Proc. ACM/IEEE Design Automation Conf., 1991, pp. 2–7.
-
(1991)
Proc. ACM/IEEE Design Automation Conf.
, pp. 2-7
-
-
Gebotys, C.H.1
Elmasry, M.I.2
-
14
-
-
84941434762
-
Architectural partitioning for systems level design of integrated circuits
-
Carnegie Mellon Univ., Pittsburgh, PA, CMUCAD-89-27
-
E. D. Lagnese, “Architectural partitioning for systems level design of integrated circuits,” Ph.D. dissertation, Carnegie Mellon Univ., Pittsburgh, PA, CMUCAD-89-27, 1989.
-
(1989)
Ph.D. dissertation
-
-
Lagnese, E.D.1
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