Estimating Architectural Resources and Performance for High-Level Synthesis Applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 1, Issue 2, 1993, Pages 175-190

  Sharma, Alok ^a   Jain, Rajiv ^b  

^a Amdahl Corporation   (United States)

^b UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED LOGIC DESIGN; COMPUTER CIRCUITS; LOGIC DESIGN;

ARCHITECTURAL SYNTHESIS; DATA FLOW GRAPHS; INTERCONNECTS;

COMPUTER ARCHITECTURE;

EID: 0027612296     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.238417     Document Type: Article

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