Performance-Driven Interconnection Optimization for Microarchitecture Synthesis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 2, 1994, Pages 137-149

  Jiang, Yi Min ^a   Lee, Tsing Fa ^a   Hwang, Ting Ting ^a   Lin, Youn Long ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

High Level Synthesis; Microarchitecture Level Design; Performance Driven Interconnection Synthesis

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; DATA TRANSFER; HEURISTIC PROGRAMMING; LARGE SCALE SYSTEMS; LINEAR PROGRAMMING; MATHEMATICAL MODELS; OPTIMIZATION; PERFORMANCE; STORAGE ALLOCATION (COMPUTER);

DELAY TIME; HIGH LEVEL SYNTHESIS; MICROARCHITECTURE LEVEL DESIGN; PERFORMANCE CONSTRAINED BINDING; PERFORMANCE DRIVEN INTERCONNECTION SYNTHESIS; RESOURCE CONSTRAINED BINDING;

ELECTRIC NETWORK SYNTHESIS;

EID: 0028374229     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.259938     Document Type: Article

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