Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint

Proceedings of the International Symposium on Low Power Design

Volumn , Issue , 1995, Pages 167-172

  Borah, Manjit ^a   Owens, Robert Michael ^a   Irwin, Mary Jane ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; CONSTRAINT THEORY; ELECTRIC LOADS; ELECTRIC LOSSES; ELECTRIC POWER SUPPLIES TO APPARATUS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; OPTIMIZATION; SHORT CIRCUIT CURRENTS; TRANSISTORS;

POWER DELAY; TRANSISTOR SIZING;

CMOS INTEGRATED CIRCUITS;

EID: 0029178885     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/224081.224111     Document Type: Conference Paper

References (17)