Low power tradeoffs in signal processing hardware primitives

IEEE Workshop on VLSI Signal Processing, Proceedings

Volumn , Issue , 1994, Pages 276-285

  Nagendra, Chetana ^a   Owens, Robert Michael ^a   Irwin, Mary Jane ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CAPACITANCE; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC LOSSES; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; MOBILE TELECOMMUNICATION SYSTEMS; PARALLEL PROCESSING SYSTEMS; POWER CONTROL; REAL TIME SYSTEMS; TRANSISTORS;

LINEAR TIME RIPPLE CARRY ADDERS; LOOKAHEAD ADDERS; MANCHESTER CARRY CHAIN ADDERS; PARALLEL ADDERS;

DIGITAL SIGNAL PROCESSING;

EID: 0028746383     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)